18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

Single Supply, 24-Bit, Sigma-Delta ADC with 10 V and 0 mA to 20 mA Inputs, Open Wire Detection Features: Tested for robustness per: IEC6100-4-2, IEC6100-4-3, IEC6100-4-4, IEC6100-4-5, IEC6100-4-6, CISPR 11 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 μs settling) 16 noise free bits at 1 kSPS per channel 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 4 differential or 8 single-ended Pin absolute maximum rating ±50 V Absolute input pin voltage up to ±20 V ≥1 MΩ impedance ±0.06% accuracy at 25°C Open wire detection 0 mA to 20 mA inputs, 4 single-ended Pin absolute maximum rating ±50 mA Input range from −0.5 mA to +24 mA 60 Ω impedance ±0.08% accuracy at 25°C On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Internal or external clock Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total IDD = 3.9 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible

Single-Supply, Multichannel, 125 kSPS, 24-Bit, Sigma-Delta ADC with 10 V Inputs Features:24-bit ADC with integrated AFEFast and flexible output rate: 2.5 SPS to 125 kSPSChannel scan data rate of 24,845 SPS per channel (40.25 s settling)85 dB common mode rejection of 50 Hz and 60 Hz at 20 SPS per channel10 V inputs, either 8 differential or 16 single-endedVIN pin absolute maximum rating 65 VAbsolute input pin voltage up to 20 VMinimum 1 M impedanceOn-chip 2.5 V reference0.12% initial accuracy at 25C, 5 ppm/C (typical) driftInternal or external clockPower suppliesAVDD = 4.5 V to 5.5 VIOVDD = 2 V to 5.5 VTotal current consumption AVDD + IOVDD (IDD) = 10.4 mATemperature range: 40C to +105C3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)SPI, QSPI, MICROWIRE, and DSP compatible

Fully Accurate 12-Bit VOUT nanoDAC SPI Interface 4.5 V to 5.5 V in a TSSOP Features: Low power dual 12-/14-/16-bit DAC, ±1 LSB INL Individual voltage reference pins Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale Power down to 400 nA at 5 V 3 power-down functions Per channel power-down Low glitch upon power-up Hardware power-down lockout capability Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option 14-lead TSSOP

256 Position SPI/I2C Selectable Digital Potentiometer Features: 256-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm × 4.9 mm) package Pin selectable SPI/I2C compatible interface Extra package address decode pin AD0 Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/°C Low power, IDD = 8 μA Wide operating temperature −40°C to +125°C SDO output allows multiple device daisy-chaining Evaluation board available

3000 V/S, 35mW Current Feedback Quad Amplifier Features: High speed 250 MHz -3 dB bandwidth (G = +1) 3000 V/µs slew rate 21 ns settling time to 0.1% 1.8 ns rise time for 2 V step Low power 3.5 mA/amp power supply Current (35 mW/amp) Single supply operation Fully specified for +5 V supply High output current of 50 mA Good video specifications (RL = 150 Ω, G = +2) Gain flatness 0.1 dB to 30 MHz 0.04% differential gain error 0.10° differential phase error Low distortion –78 dBc THD at 5 MHz –61 dBc THD at 20 MHz Available in a 14-lead SOIC

160 MHz Rail-to-Rail Amplifier with Disable Features: Fully specified for +3 V, +5 V and ±5 V Supplies Output Swings Rail to Rail Input Voltage Range Extends 200 mV Below Ground No Phase Reversal with Inputs 1 V Beyond Supplies Disable/Power-Down Capability Low Power of 5.2 mA (26 mW on 5 V) High Speed and Fast Settling on 5 V: 160 MHz -3 dB Bandwidth (G = +2) 160 V/µs Slew Rate 30 ns Settling Time to 0.1% Good Video Specifications (RL = 150 Ω, G = +2) Gain Flatness of 0.1 dB to 30 MHz 0.03% Differential Gain Error 0.03° Differential Phase Error Low Distortion -69 dBc Worst Harmonic @ 10 MHz Outstanding Load Drive Capability Drives 50 mA 0.5 V from Supply Rails Cap Load Drive of 45 pF

Triple Differential Receiver with Adjustable Line Equalization Features: Compensates cables to 300 meters for wideband video Fast rise and fall times 4.9 ns with 2 V step at 150 meters of UTP cable 8.0 ns with 2 V step at 300 meters of UTP cable 55 dB peak gain at 100 MHz Two frequency response gain adjustment pins High frequency peaking adjustment (VPEAK) Broadband flat gain adjustment (VGAIN) Pole location adjustment pin (VPOLE) Compensates for variations between cables Can be optimized for either UTP or coaxial cable DC output offset adjust (VOFFSET) Low output offset voltage: 24 mV Compensates both RGB and YPbPr Two on-chip comparators with hysteresis Can be used for common-mode sync extraction Available in 40-lead, 6 mm × 6 mm LFCSP

Low Cost 270 MHz Differential Receiver Amplifier Features: High Speed AD8130: 270 MHz, 1090 V/µs @ G = +1 AD8129: 200 MHz, 1060 V/µs @ G = +10 High CMRR 94 dB min, dc to 100 kHz 80 dB min @ 2 MHz 70 dB @ 10 MHz Low noise AD8130: 12.5 nV/√Hz AD8129: 4.5 nV/√Hz High input impedance: 1 MΩ differential Input common-mode range ±10.5 V Low distortion, 1 V p-p @ 5 MHz: AD8130, -79 dBc worst harmonic @ 5 MHz AD8129, -74 dBc worst harmonic @ 5 MHz User-adjustable gain No external components for G = +1 Power supply range +4.5 V to ±12.6 V Power-down

Triple Differential Driver for Wideband Video Features:Triple high speed fully differential driver700 MHz, 3 dB, 2 V p-p bandwidth (AD8146/AD8148)600 MHz, 3 dB, 2 V p-p bandwidth (AD8147)200 MHz, 0.1 dB, 2 V p-p bandwidth3000 V/s slew rate Fixed gain (AD8146/AD8147: G = 2, AD8148: G = 4) Differential or single-ended input to differential output Can be used as differential-to-differential receiver Drives one or two 100 UTP cables Adjustable output common-mode voltage (AD8146) Internal common-mode feedback network Output balance error 50 dB @ 50 MHz On-chip, sync-on common-mode encoding (AD8147/AD8148) Output pull-down feature for line isolation Low power: 57 mA @ 5 V for 3 drivers (AD8146) Wide supply voltage range: +5 V to 5 V Available in a small 4 mm 4 mm LFCSP