Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel, 11-bit resolution 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1  Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

12-Bit, 1 GSPS/500 MSPS JESD204B,Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs 1.5 W total power per channel at 1 GSPS (default settings) SFDR 79 dBFS at 340 MHz (1 GSPS) 85 dBFS at 340 MHz (500 MSPS) SNR 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS, 1 GSPS) 65.6 dBFS at 340 MHz (AIN = −1.0 dBFS, 500 MSPS) ENOB = 10.4 bits at 10 MHz (1 GSPS) DNL = ±0.16 LSB; INL = ±0.35 LSB (1 GSPS) Noise density −151 dBFS/Hz (1 GSPS) −150 dBFS/Hz (500 MSPS) 1.25 V, 2.5 V, and 3.3 V dc supply operation Low swing full-scale input 1.34 V p-p typical (1 GSPS) 1.63 V p-p typical (500 MSPS) No missing codes Internal ADC voltage reference Flexible termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 2 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation Differential clock input Optional decimate by 2 DDC per channel Differential clock input Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither

14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B Subclass 0 or Subclass 1 coded serial digital outputs Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and 250 MSPS Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS Total power consumption: 711 mW at 250 MSPS 1.8 V supply voltages Integer 1-to-8 input clock divider Sample rates of up to 250 MSPS IF sampling frequencies of up to 400 MHz Internal analog-to-digital converter (ADC) voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS) 95 dB channel isolation/crosstalk Serial port control Energy saving power-down modes

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

Dual Low Power, High Speed JFET Operational Amplifier Features: Low supply current: 250 μA/amp maximum High slew rate: 9 V/μs Bandwidth: 3.5 MHz typical Low offset voltage: 1 mV maximum @ 25°C Low input bias current: 20 pA maximum @ 25°C CMRR: 90 dB typical Fast settling time Unity gain stable

SHARC DIGITAL SIGNAL PROCESSORS;

SHARC DIGITAL SIGNAL PROCESSORS;

LDO VOLTAGE REGULATORS;

LDO VOLTAGE REGULATORS;