2.7 V to 5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead MSOP Features:Specified for VDD of 2.7 V to 5.25 VFlexible power/throughput rate managementShutdown mode: 1 A maxOne or two single-ended inputsSerial interface: SPI/QSPI/MICROWIRE/DSP compatible8-lead narrow SOIC and MSOP packages

14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP Features: 14-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR) SINAD: 85 dB @ 20 kHz THD: −100 dB @ 20 kHz Pseudo differential analog input range 0 V to VREF with VREF up to VDD No pipeline delay See Data Sheet for Additional Information

50 V, 130 kHz, 32.5 A per Channel, Robust, Over-The-Top, Precision Op Amp Features: Ultrawide common-mode input range: −VS − 0.1 V to −VS + 70 V Wide power supply voltage range: +3 V to +50 V (to ±25 V for PSRR) Low power supply current: 32.5 μA (typical) Low input offset voltage: ±60 μV maximum Low input offset voltage drift: ±1 μV/°C maximum (B grade) Low input voltage noise 6 Hz typical 1/f noise corner 1000 nV p-p typical at 0.1 Hz to 10 Hz GBP: 130 kHz typical for fTEST = 250 Hz Slew rate: 0.1 V/μs typical at ΔVOUT = 4 V Low power supply current shutdown: 20 μA maximum Low input offset current: ±300 pA maximum Large signal voltage gain: 120 dB minimum for ΔVOUT = 3.5 V CMRR: 120 dB minimum at VCM = −0.1 V to +70 V PSRR: 123 dB minimum at VSY = +3 V to ±25 V Input overdrive tolerant with no phase reversal ±2 kV HBM and ±1.25 kV FICDM Wide temperature range: −55°C to +150°C (H grade) Shutdown feature available for single 6-lead TSOT and dual 10-lead LFCSP packages

Bridge Sensor Signal Conditioner IC with LIN Interface, Nonlinearity Correction, Temperature Compensation Features:LIN 2.1 compliant interface (bridge sensor signal, temperature)Digitally programmable gain and offset voltage adjustmentGain range from 2.94 V/V to 971.10 V/VSensor temperature compensation (first- or second-order)Sensor nonlinearity correction (first- or second-order)Internal or external temperature sensor compensationEEPROM nonvolatile memory for calibration dataHigh system accuracy: 0.1% FSR over temperatureEMC and EMI protectionFault protection for open circuits and short circuits4 mm 4 mm, 20-lead LFCSP6 V to 18 V supply operation40C to +150C operating temperature rangeAEC-Q100 qualified for automotive applications

16-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common range High common-mode rejection Single-ended to differential conversion 2.048 V input range with 4.096 V REFBUF Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball BGA package 4× footprint reduction versus discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL: 0.4 LSB typical, 1 LSB maximum SINAD: 89 dB typical at 1 kHz THD: 115 dB at 1 kHz, 106 dB at 400 kHz Gain error: 0.005% FS typical Gain error drift: 1 ppm/C maximum On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: 40C to +85C

18-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common-mode voltage range High common-mode rejection Single-ended to differential conversion Pin selectable input range with overrange Input ranges with 4.096 V REFBUF: ±10 V, ±5 V, ±4.096 V, ±2.5 V, and ±1.5 V Gain/attenuation options: 0.37, 0.73, 0.87, 1.38, and 2.25 Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball CSP_BGA package 2.5× footprint reduction vs. discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL error: ±3.1 ppm typical, ±6.2 ppm maximum (Gain = 0.73, gain = 0.87, gain = 1.38, gain = 2.25) SINAD: 90.4 dB typical at 20 kHz (gain = 0.73) THD: −117 dB at 1 kHz, −110 dB at 100 kHz (gain = 0.73) Gain error: ±0.005%FS typical Gain error drift: ±0.13 ppm/°C typical On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: −40°C to +85°C

SigmaDSP Compact Digital Audio Processor with Extended Internal Memory Features: Qualified for automotive applications High performance SigmaDSP core enables low latency and audio applications Active Noise Cancellation (ANC) Echo-Canceller and Noise Reduction (ECNR) Surround sound algorithms Features SigmaStudio, a proprietary graphical Integrated Development Environment (IDE), for the development of custom signal flows Comprehensive Toolbox of pre-defined building blocks Faster design time with proven solutions Intuitive system design 294.912 MHz, 32-bit SigmaDSP core at 1.2 V 24 kWords of program memory 80 kWords of parameter/data RAM 6144 SIMD instructions per sample at 48 kHz 1600 ms digital audio delay pool at 48 kHz Audio I/O and routing 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital I/O up to a sample rate of 192 kHz Flexible configuration of I2S, left and right justified, and up to 16-channel TDM formats on serial data pins 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and 139 dB dynamic range Stereo S/PDIF input and output at 192 kHz Four PDM microphone input channels Multichannel, byte addressable TDM serial ports Clock oscillator for generating master clock from crystal Integer PLL and flexible clock generators Integrated die temperature sensor I2C and SPI control interfaces (both slave and master) Standalone operation Self-boot from serial EEPROM 6-channel, 10-bit SAR auxiliary control ADC 14 multipurpose pins for digital controls and outputs On-chip regulator for generating 1.2 V from 1.8 V to 3.3 V supply 72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm exposed pad Temperature range: −40°C to +105°C

Three ADCs, One DAC, Low Power Codec with Audio DSPs Features: Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing Tensilica HiFi 3z DSP core Quad MAC per cycle: 24 x 24-bit multiplier and 64-bit accumulator Flexible power operation mode: 24.576 MHz, 49.152 MHz, 73.728 MHz, and 98.304 MHz 336 kB total memory JTAG debug and trace Low latency, 24-bit ADCs and DAC 106 dB SNR (signal through ADC with A-weighted filter) 110 dB combined SNR (signal through DAC and headphone with A-weighted filter) Programmable double precision MAC engine for maximum 24-stage equalizer Serial port sample rates from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 3 differential or single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs Analog differential audio output, configurable as either line output or headphone drive 2 PDM output channels PLL supporting any input clock rate from 30 kHz to 36 MHz 4 channel asynchronous sample rate converters (ASRCs) 2, 16-channel serial audio ports supporting I2S, left justified, right justified, or up to TDM16 (TDM12 in Turbo mode) 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.85 V to 1.21 V Headphone HPVDD at 1.8 V typical Headphone HPVDD_L at 1.2 V to HPVDD Control/communication interfaces I2C, SPI, or UART control ports Master quad SPI (QSPI) UART communication port Self-boot from QSPI flash Flexible GPIO and IRQ 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP

8 Channel, PDM to I2S/TDM Converter Features: 8 channels of PDM audio inputs from digital microphones 16×, 32×, or 64× decimation ratio of PDM to PCM audio data 24-bit resolution to support high sound pressure level (SPL) microphones 126 dB A-weighted SNR 4 kHz to 192 kHz output sampling rate Bit clock rates of 64×, 128×, 192×, 256×, 384×, or 512× the output sampling rate Dual output PDM clocks Automatic PDM clock generation Automatic power-down when BCLK removed Selectable I2C control or hardware mode operation 1.2 mA DVDD operating current for 8 channels at 48 kHz frequency sampling rate and 1.8 V supply Slave I2S or TDM output interface Up to TDM-16 supported Configurable TDM slot routing and sizes I/O supply voltage from 1.70 V to 3.63 V DVDD supply voltage from 1.10 V to 1.98 V <5 μA typical DVDD shutdown current 16-lead, 3 mm × 3 mm, 0.50 mm pitch LFCSP Power-on reset

18-Cell Battery Monitor with Daisy Chain Interface Features: Measures up to 18 battery cells in series 3 mV maximum total measurement error Stackable architecture for high voltage systems Built-in isoSPI interface 1 Mb isolated serial communications Uses a single twisted pair, up to 100 meters Low EMI susceptibility and emissions Bidirectional for broken wire protection 290 μs to measure all cells in a system Synchronized voltage and current measurement 16-bit Δ-Σ ADC with programmable third-order noise filter Passive cell balancing up to 200 mA (maximum) with programmable pulsewidth modulation 9 general purpose digital I/O or analog inputs Temperature or other sensor inputs Configurable as an I2C or SPI master 6 μA sleep mode supply current 64-lead LQFP_EP package