MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU Features: High resolution Σ-Δ ADCs 2 independent 24-bit ADCs Up to 10 ADC input channels on all devices 24-bit no missing codes 22-bit rms (19.5 bit p-p) effective resolution Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled Memory 62-kbyte on-chip Flash/EE program memory 4-kbyte on-chip Flash/EE data memory Flash/EE, 100-year retention, 100 kcycle endurance 3 levels of Flash/EE program memory security In-circuit serial download (no external hardware) High speed user download (5 sec) 2304 bytes on-chip data RAM See data sheet for additional features

Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Features: EEMBC ULPMark™-CP score (3 V): 189 Ultra low power active and hibernate modes Active mode dynamic current: 41 μA/MHz (typical) Flexi mode: 400 μA (typical) Hibernate mode: 0.65 μA (typical) Shutdown mode: 50 nA (typical) Shutdown mode (fast wake-up): 0.20 μA (typical) ARM Cortex-M4F processor at 52 MHz with FPU, MPU, ITM with SWD interface Power management Single-supply operation (connected to VBAT pins): 1.74 V to 3.6 V Optional buck converter for improved efficiency Memory options 512 kB of embedded flash memory with ECC 4 kB of cache memory to reduce active power 128 kB of configurable system SRAM with parity Safety Watchdog with dedicated on-chip oscillator Hardware CRC with programmable polynomial Multiparity bit protected SRAM ECC protected embedded flash Security Hardware cryptographic accelerator supporting AES-128, AES-256, and SHA-256 Protected key storage in flash, SHA-256-based keyed HMAC and key wrap and unwrap User code protection TRNG Digital peripherals 3 SPI interfaces to enable glueless interface to sensors, radios, and converters 1 I2C and 2 UART peripheral interfaces SPORT for natively interfacing with converters and radios Programmable GPIOs (44 in LFCSP and 51 in WLCSP) 3 general-purpose timers with PWM support RGB timer for driving RGB LED RTC0 for time keeping RTC1 with SensorStrobe and time stamping Programmable beeper 27-channel DMA controller Clocking features 26 MHz clock: on-chip oscillator, external crystal oscillator, SYS_CLKIN for external clock, and integrated PLL 32 kHz clock: on-chip oscillator and low power crystal oscillator Clock fail detection for external crystals Analog peripherals 12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital comparator

Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Features: EEMBC ULPMark™-CP score (3 V): 189 Ultra low power active and hibernate modes Active mode dynamic current: 41 μA/MHz (typical) Flexi mode: 400 μA (typical) Hibernate mode: 0.65 μA (typical) Shutdown mode: 50 nA (typical) Shutdown mode (fast wake-up): 0.20 μA (typical) ARM Cortex-M4F processor at 52 MHz with FPU, MPU, ITM with SWD interface Power management Single-supply operation (connected to VBAT pins): 1.74 V to 3.6 V Optional buck converter for improved efficiency Memory options 512 kB of embedded flash memory with ECC 4 kB of cache memory to reduce active power 128 kB of configurable system SRAM with parity Safety Watchdog with dedicated on-chip oscillator Hardware CRC with programmable polynomial Multiparity bit protected SRAM ECC protected embedded flash Security Hardware cryptographic accelerator supporting AES-128, AES-256, and SHA-256 Protected key storage in flash, SHA-256-based keyed HMAC and key wrap and unwrap User code protection TRNG Digital peripherals 3 SPI interfaces to enable glueless interface to sensors, radios, and converters 1 I2C and 2 UART peripheral interfaces SPORT for natively interfacing with converters and radios Programmable GPIOs (44 in LFCSP and 51 in WLCSP) 3 general-purpose timers with PWM support RGB timer for driving RGB LED RTC0 for time keeping RTC1 with SensorStrobe and time stamping Programmable beeper 27-channel DMA controller Clocking features 26 MHz clock: on-chip oscillator, external crystal oscillator, SYS_CLKIN for external clock, and integrated PLL 32 kHz clock: on-chip oscillator and low power crystal oscillator Clock fail detection for external crystals Analog peripherals 12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital comparator

Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Features: EEMBC ULPMark™-CP score (3 V): 189 Ultra low power active and hibernate modes Active mode dynamic current: 41 μA/MHz (typical) Flexi mode: 400 μA (typical) Hibernate mode: 0.65 μA (typical) Shutdown mode: 50 nA (typical) Shutdown mode (fast wake-up): 0.20 μA (typical) ARM Cortex-M4F processor at 52 MHz with FPU, MPU, ITM with SWD interface Power management Single-supply operation (connected to VBAT pins): 1.74 V to 3.6 V Optional buck converter for improved efficiency Memory options 512 kB of embedded flash memory with ECC 4 kB of cache memory to reduce active power 128 kB of configurable system SRAM with parity Safety Watchdog with dedicated on-chip oscillator Hardware CRC with programmable polynomial Multiparity bit protected SRAM ECC protected embedded flash Security Hardware cryptographic accelerator supporting AES-128, AES-256, and SHA-256 Protected key storage in flash, SHA-256-based keyed HMAC and key wrap and unwrap User code protection TRNG Digital peripherals 3 SPI interfaces to enable glueless interface to sensors, radios, and converters 1 I2C and 2 UART peripheral interfaces SPORT for natively interfacing with converters and radios Programmable GPIOs (44 in LFCSP and 51 in WLCSP) 3 general-purpose timers with PWM support RGB timer for driving RGB LED RTC0 for time keeping RTC1 with SensorStrobe and time stamping Programmable beeper 27-channel DMA controller Clocking features 26 MHz clock: on-chip oscillator, external crystal oscillator, SYS_CLKIN for external clock, and integrated PLL 32 kHz clock: on-chip oscillator and low power crystal oscillator Clock fail detection for external crystals Analog peripherals 12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital comparator

Precision Analog Microcontroller, 16-Bit Analog Input/Output with MDIO Interface, Arm Cortex-M33 Features: Analog input/output Multichannel, 16-bit, 2 MSPS ADC Up to 16 external channels On-chip die temperature monitor 4 power monitor channels 4 PGA/TIA channels supporting voltage and current measurements Fully differential and single-ended modes 0 V to VREF analog input range 12-bit voltage output DACs 8× 0 V to 2.5 V, 1 kΩ load 4× 0 V to 2.5 V, 2.5 kΩ load On-chip low drift voltage reference, 1.25 V or 2.5 V Buffered 1.25 V or 2.5 V output 4 voltage comparators Microcontroller 32-bit Arm Cortex-M33 core, 32-bit RISC architecture, FPU Serial wire port supports code download and debug Clocking options 16 MHz on-chip oscillator 160 MHz PLL output with programmable divider External clock source Memory 2× 512 kB independent Flash/EE memories 10,000-cycle Flash/EE endurance 20-year Flash/EE retention 128 kB SRAM with ECC Software triggered, in circuit reprogrammability via MDIO or I2C On-chip peripherals 2× UART, 3× SPI, 3× I2C serial input/output Multilevel voltage (3.3 V, 1.8 V, 1.2 V) GPIOs MDIO slave up to 10 MHz 5 general-purpose timers Wake-up timer (WUTs) Watchdog timers (WDTs) 32-element PLA 16-bit PWM 10 external Interrupts Power Multiple supplies: 3.3 V for voltage DACs and ADCs, and 3.3 V, 1.8 V, or 1.2 V for digital inputs/outputs Flexible operating modes for low power applications Packages and temperature range 5 mm × 5 mm 81-ball CSP_BGA and 3.46 mm × 3.46 mm 64-ball WLCSP BGA package uses ULA molding compounds Fully specified for −40°C to +105°C operation Tools Low cost quick start development system Full third-party support  

Silicon SPDT Switch, Reflective, 35 GHz to 44 GHz Features:Reflective design Low insertion loss: 1.8 dB at 44 GHz High isolation: 28 dB at 44 GHz High input linearity 0.1 dB power compression (P0.1dB): 37 dBm Third-order intercept (IP3): 52 dBm High RF power handling: 28 dBm average 36 dBm peak Single supply operation: 3.3V Internal negative voltage generator (NVG) RF settling time (0.1 dB final RF output): 45 ns 20-terminal, 3 mm × 3 mm, land grid array package Pin compatible with the ADRF5300: 24 GHz - 32 GHz

Dual-Channel, 3.7 GHz to 5.3 GHz, Receiver Front End Features: Integrated dual-channel RF front end 2-stage LNA and high power SPDT switch On-chip bias and matching Single supply operation Gain High gain mode: 33 dB typical at 4.6 GHz Low gain mode: 18 dB typical at 4.6 GHz Low noise figure High gain mode: 1.6 dB typical at 4.6 GHz Low gain mode: 1.6 dB typical at 4.6 GHz High channel to channel isolation  Between RxOUT-ChA and RxOUT-ChB: 45 dB typical Between TERM-ChA and TERM-ChB: 53 dB typical  Low insertion loss: 0.5 dB typical at 4.6 GHz High power handling at TCASE = 105°C Full lifetime LTE average power (9 dB PAR): 40 dBm Single event (<10 sec operation) LTE average power (9 dB PAR): 43 dBm High OIP3: 31 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5 V Low gain mode: 36 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 40-lead, 6 mm × 6 mm LFCSP 

0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz Features:Ultrawideband frequency range: 100 MHz to 40 GHz Attenuation range: 0.5 dB steps to 31.5 dB Low insertion loss with impedance match 2.1 dB up to 18 GHz 2.9 dB up to 26 GHz 4.8 dB up to 40 GHz Attenuation accuracy with impedance match ±(0.10 + 1.0% of attenuation state) up to 18 GHz ±(0.15 + 0.8% of attenuation state) up to 26 GHz ±(0.35 + 2.5% of attenuation state) up to 40 GHz Typical step error with impedance match ±0.18 dB up to 18 GHz ±0.23 dB up to 26 GHz ±0.51 dB up to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 27 dBm IP3: 50 dBm typical High RF input power handling: 27 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF settling time (0.1 dB of final RF output): 250 ns 24-terminal, 4 mm × 4 mm LGA package Pin compatible with ADRF5720, low frequency cutoff version

2 dB LSB, 4-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz Features: Ultrawideband frequency range: 100 MHz to 40 GHz Attenuation range: 2 dB steps to 30 dB Low insertion loss 1.7 dB to 18 GHz 2.2 dB to 26 GHz 3.5 dB to 40 GHz Attenuation accuracy ±(0.1 + 2.0%) of attenuation state up to 18 GHz ±(0.2 + 2.5%) of attenuation state up to 26 GHz ±(0.5 + 10.0%) of attenuation state up to 40 GHz High RF input power handling: 26 dBm average, 30 dBm peak Tight distribution in relative phase Typical step error ±0.15 dB to 18 GHz ±0.20 dB to 26 GHz ±0.60 dB to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 26 dBm IP3: 50 dBm typical No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 230 ns 2.5 mm × 2.5 mm, 16-terminal LGA package Pin compatible with ADRF5721, low frequency cutoff version

Dual Narrow/Wideband RF Transceiver Features: 2 2 highly integrated transceiver Frequency range of 30 MHz to 6000 MHz Transmitter and receiver bandwidth from 12 kHz to 40 MHz Two fully integrated, fractional-N, RF synthesizers LVDS and CMOS synchronous serial data interface options Low power monitor and sleep modes Multichip synchronization capabilities Fast frequency hopping Dynamic profile switching for dynamic data rates and sample rates Fully programmable via a 4-wire SPI 12 mm 12 mm, 196-ball CSP_BGA