The ADXL362 is an ultralow power, 3-axis MEMS accelerometer that consumes less than 2 μA at a 100 Hz output data rate and 270 nA when in motion triggered wake-up mode. Unlike accelerometers that use power duty cycling to achieve low power consumption, the ADXL362 does not alias input signals by undersampling; it samples the full bandwidth of the sensor at all data rates.The ADXL362 always provides 12-bit output resolution; 8-bit formatted data is also provided for more efficient single-byte transfers when a lower resolution is sufficient. Measurement ranges of ±2 g, ±4 g, and ±8 g are available, with a resolution of 1 mg/LSB on the ±2 g range. For applications where a noise level lower than the normal 550 μg/√Hz of the ADXL362 is desired, either of two lower noise modes (down to 175 μg/√Hz typical) can be selected at minimal increase in supply current.In addition to its ultralow power consumption, the ADXL362 has many features to enable true system level power reduction. It includes a deep multimode output FIFO, a built-in micropower temperature sensor, and several activity detection modes including adjustable threshold sleep and wake-up operation that can run as low as 270 nA at a 6 Hz (approximate) measurement rate. A pin output is provided to directly control an external switch when activity is detected, if desired. In addition, the ADXL362 has provisions for external control of sampling time and/or an external clock.The ADXL362 operates on a wide 1.6 V to 3.5 V supply range, and can interface, if necessary, to a host operating on a separate, lower supply voltage. The ADXL362 is available in a 3 mm × 3.25 mm × 1.06 mm package.APPLICATIONS Hearing aids Home healthcare devices Motion enabled power save switches Wireless sensors Motion enabled metering devices

The SSM3302 is a fully integrated, high efficiency, stereo Class-D audio amplifier. The application circuit requires minimal externalcomponents and operates from a single 7 V to 18 V supply. The device is capable of delivering 2 × 10 W of continuous output power into a 4 Ω load (or 2 × 8 W into 8 Ω) with 98 dB. Spread spectrum pulse density modulation (PDM) is used toprovide lower EMI radiated emissions compared with other Class-D architectures. The SSM3302 includes an optional modulation select pin (ultralow EMI emission mode) that significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. The SSM3302 can pass FCC Class-B emissions testing with an unshielded 20 inch cable using common-mode choke-based filtering.The fully differential input of the SSM3302 provides excellent rejection of common-mode noise on the input. The device also includes a highly flexible gain select pin that only requires one series resistor to choose a gain between 9 dB and 24 dB, with no change to the input impedance. The benefit of this is to improve gain matching between multiple SSM3302 devices within a single application compared with using external resistors to set gain.The SSM3302 includes an integrated voltage regulator thatgenerates a 5 V rail.The SSM3302 has a micropower shutdown mode with a typical shutdown current of 10 μA. Shutdown is enabled by applying a logic low to the SD pin. The device also includes pop-and-click suppression circuitry that minimizes voltage glitches at the output during turn on and turn off, reducing audible noise during activation and deactivation.Other included features to simplify system level integration of the SSM3302 are input low-pass filtering to suppress out-ofband DAC noise interference to the pulse density modulator, fixed input impedance to simplify component selection across multiple platform production builds, and a thermal warning indicator pin.The SSM3302 is specified over the commercial temperaturerange (−40°C to +85°C). It has built-in thermal shutdown andoutput short-circuit protection. It is available in a halide-free,40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP).APPLICATIONS Mobile computing Flat panel televisions Media docking stations Portable electronics Sound bars

The ADR3412 / ADR3420 / ADR3425 / ADR3430 / ADR3433 / ADR3440 / ADR3450 are low-cost, low-power, high precision voltage references, featuring ± 0.1% initial accuracy, low operating current and low output noise in a small SOT23 package. For high accuracy, output voltage and temperature coefficient are trimmed digitally during final assembly using Analog Devices’ proprietary Digi-Trim® technology. Stability and reliability are further improved by the devices’ low output voltage hysteresis and low long-term output voltage drift.Furthermore, the low operating current of the device (100 μA max) facilitates usage in low-power devices, while its low output noise helps maintain signal integrity in critical signal processing systems.These CMOS are available in a wide range of output voltages, all of which are specified over the industrial temperature range of −40°C to +125 °C.APPLICATIONS Precision data acquisition systems Industrial instrumentation Medical devices Battery-powered devices

The ADRF6702 provides a quadrature modulator and synthesizer solution within a small 6 mm × 6 mm footprint while requiring minimal external components.The ADRF6702 is designed for RF outputs from 1200 MHz to 2400 MHz. The low phase noise VCO and high performance quadrature modulator make the ADRF6702 suitable for next generation communication systems requiring high signal dynamic range and linearity. The integration of the IQ modulator, PLL, and VCO provides for significant board savings and reduces the BOM and design complexity.The integrated fractional-N PLL/synthesizer generates a 2× fLO input to the IQ modulator. The phase detector together with an external loop filter is used to control the VCO output. The VCO output is applied to a quadrature divider. To reduce spurious components, a sigma-delta (Σ-Δ) modulator controls the programmable PLL divider.The IQ modulator has wideband differential I and Q inputs, which support baseband as well as complex IF architectures. The single-ended modulator output is designed to drive a 50 Ω load impedance and can be disabled.The ADRF6702 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP package. Performance is specified from −40°C to +85°C. A lead-free evaluation board is available.APPLICATIONS Cellular communications systems        GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE Broadband wireless access systems Satellite modems

The ADRF6750 is a highly integrated quadrature modulator, frequency synthesizer, and programmable attenuator. The device covers an operating frequency range from 950 MHz to 1575 MHz for use in satellite, cellular and broadband communications.The ADRF6750 modulator includes a high modulus fractional-N frequency synthesizer with integrated VCO, providing better than 1 Hz frequency resolution, and a 47 dB digitally controlled output attenuator with 1 dB steps.Control of all the on-chip registers is through a user-selected SPI interface or I2C interface. The device operates from a single power supply ranging from 4.75 V to 5.25 V.

The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21478 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21478 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21478 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21479 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21479 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21479 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs. Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21479 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21479 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21479 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs. Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The SHARC ADSP-21489 is one of two new members of the fourth generation of SHARC® Processors that now includes the ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21489 offers the highest performance–450 MHz/2700 MFLOPs–in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The SHARC ADSP-21489 is one of two new members of the fourth generation of SHARC® Processors that now includes the ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21489 offers the highest performance–450 MHz/2700 MFLOPs–in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).