3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Parallel Sampling ADC Features:Specified for VDD of 3 V to 5.5 V Read-Only Operation AD7854200 kSPS; AD7854L100 kSPS System and Self-Calibration Flexible Parallel Interface12-Bit Parallel/8-Bit Parallel (AD7854) 28-Lead DIP, SOIC and SSOP Packages (AD7854) Low Power:- Normal OperationAD7854: 15 mW (VDD = 3 V)AD7854L: 5.5 mW (VDD = 3 V)- Automatic Power-Down AfterConversion (25 W)AD7854: 1.3 mW 10 kSPSAD7854L: 650 W 10 kSPS

5V, 12-Bit, Serial 220 kSPS ADC in a 8-Lead Package Features: Fast 12-Bit ADC with 220 kSPS Throughput Rate 8-Lead SOIC Single 5 V Supply Operation High Speed, Flexible, Serial Interface that Allows Interfacing to 3 V Processors On-Chip Track/Hold Amplifier Selection of Input Ranges: ±10 V for AD7898-10 ±2.5 V for AD7898-3 High Input Impedance Low Power: 22.5 mW Max

5 V Single Supply 14-Bit 400 kSPS ADC Features: Fast (2.2 µs) 14-Bit ADC 400 kSPS Throughput Rate 0.3 µs Track/Hold Acquisition Time Single Supply Operation High-Speed Parallel Interface which Also Allows Interfacing to 3 V Processors Low Power, 80 mW Typ Selection of Input Ranges: ±10 V, ±5 V and ±2.5 V 0 V to 2.5 V and 0 V to 5 V Power-Saving Mode, 20 µW Typ Overvoltage Protection on Analog Inputs Power-Down Mode via STBY Pin

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

8-Bit, 50 MSPS/80 MSPS/100 MSPS ADC Features: Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth 46.5 dB SNR at 100 MSPS with 41 MHz input 1 Vp-p Analog Input Range Single +3.0 V Supply Operation (2.7 -3.6 V) Power Down Mode: 4.2 mW

Ethernet/Gigabit Ethernet Clock Generator Features: Redundant input reference clock capability Reference monitoring function Fully integrated VCO/PLL core Jitter (rms) 0.234 ps rms jitter (10 kHz to 10 MHz) at 156.25 MHz 0.243 ps rms jitter (12 kHz to 20 MHz) at 156.25 MHz Input frequency: 19.44 MHz or 25 MHz Preset frequency translations Using a 19.44 MHz input reference 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz Using a 25 MHz input reference 25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 80 MHz, 100 MHz, 125 MHz, 133.3 MHz, 156.25 MHz, 160 MHz, 312.5 MHz Output drive formats: HSTL, LVDS, HCSL, and 1.8 V and 3.3 V CMOS Integrated loop filter (requires a single external capacitor) 2 copies of reference clock output Device configuration via strapping pins (PPRx) Space-saving 7 mm × 7 mm 48-lead LFCSP 3.3 V operation

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Features: 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply SNR 82 dBFS at 30 MHz input and 105 MSPS data rate 83 dBFS at 9.7 MHz input and 25 MSPS data rate SFDR 90 dBc at 30 MHz input and 105 MSPS data rate 95 dBc at 9.7 MHz input and 25 MSPS data rate Low power 328 mW per channel at 105 MSPS 119 mW per channel at 25 MSPS Integer 1-to-8 input clock divider See data sheet for additional featuresAD9650-EP supports defense and aerospace applications (AQEC standard) Download AD9650-EP data sheet (pdf)

Clock Drivers & Distribution 800MHz Clock Distribution IC pb free

10-Bit, 100 MSPS+ TxDAC D/A Converter Features: Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs: 2 ma to 20 mA Edge-Triggered Latches See datasheet for additional features