16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

Dual 12-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO Features: Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Low power, fine complex NCO allows carrier placement anywhere in DAC bandwidth while adding <300 mW power Auxiliary DACs allow I and Q gain matching and offset control Includes programmable I and Q phase compensation Internal digital upconversion capability Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed pad TQFP package

4T2R Direct RF Transmitter and Observation Receiver Features: Flexible reconfigurable radio common platform design Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R) RFDAC/RFADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RFCLK input option Versatile digital features Configurable digital up/down conversion (DDC and DUC) 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent 48-bit NCO per DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Auxiliary features Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins supporting different user configurations ADC clock driver with selectable divide ratios TDD power savings option and sharing ADCs SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes per each DAC and ADC JESD204B compatible with maximum 15.5 Gbps lane rate JESD204C compatible with maximum 24.75 Gbps lane rate Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

4T4R Direct RF Receiver and Transmitter Features: Flexible, reconfigurable radio common platform design Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) RF DAC/RF ADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RF clock input option Versatile digital features Selectable interpolation and decimation filters Configurable DDCs and DUCs 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC) FDUCs and FDDCs are fully bypassable 2 independent 48-bit NCOs per DUC or DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Supports real or complex digital data (8-, 12-, or 16-bit) Auxiliary features ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins support toggling between modes TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) Supports Subclass 1 Supports multidevice synchronization 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

Aerospace Monolithic JFET Input Operational Amplifier Features:Low Input Bias and Offset Currents Low Input Offset Voltage: 1.0mV typical Low Input Offset Voltage Drift: 3.0V/C typical Low Input Noise Current High Common-Mode Rejection Ratio: 100dB Low Supply Current

Precision 10V Reference Features: Pin Compatible with LH0070 and AD581 Ultralow Drift—5ppm/°C Max Slope Trimmed Output Voltage Operates in Series or Shunt Mode Output Sinks and Sources in Series Mode Very Low Noise < 1ppmP-P 0.1Hz to 10Hz > 100dB Ripple Rejection Minimum Input Voltage of 11V

Dual Output Low Noise Amplifier, 0.04 - 0.96 GHz Features: Single-ended or Balanced Output High Output IP3: +27 dBm Low Noise Figure: 3.5 dB Single Positive Supply: +5V 75 Ohm Input

HBT Vector Modulator SMT, 700 - 1000 MHz Features: Continuous Phase Control: 360° Continuous Gain Control: 40 dB Low Output Noise Floor: -162 dBm/Hz High Input IP3: +34 dBm 16 Lead 3×3mm SMT Package: 9mm2

LNA with Failsafe Bypass Mode SMT, 1700 - 2200 MHz Features: Noise Figure: 1.4 dB Output IP3: +29 dBm Gain: 17 dB Failsafe Operation: Bypass is enabled when LNA is unpowered Single Supply: +3V or +5V 16 Lead 3x3mm SMT Package: 9mm²

26 GHz, T Flip-Flop w/Reset Features: Supports Clock Frequencies up to 26 GHz Differential & Singe-Ended Operation Fast Rise and Fall Times: 18/17 ps Low Power Consumption: 270 mW typ. Propagation Delay: 95 ps Single Supply: -3.3V 16 Lead Ceramic 3×3mm SMT Package: 9mm2