DSP Microcomputer

Dual 12-Bit, LVDS Interface 500 MSPS DAC Features: High dynamic range, dual DAC parts LVDS inputs with dual-port or optional interleaved single-port operation Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF Innovative switching output stage permits usable outputs beyond Nyquist frequency LVDS inputs with dual-port or optional interleaved singleport operation See datasheet for additional features

800 MHz, Linear-in-dB VGA with AGC Detector Features: Analog variable gain range: −12 dB to +22 dB Linear-in-dB scaling: 37.5 dB/V 3 dB bandwidth: 800 MHz @ VGAIN = 0.5 V Integrated rms detector P1dB: 16 dBm @ 140 MHz Output IP3: 33 dBm @ 140 MHz Noise figure at maximum gain: 9.5 dB @ 140 MHz Input and output impedances: 50 Ω Single-supply voltage from 4.5 V to 5.5 V RoHS-compliant, 24-lead LFCSP

Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs

Complete, Quad, 14-Bit, Serial Input, Unipolar/Bipolar Voltage Output DAC Features: Complete, quad, 12-/14-/16-bit digital-to-analog converter (DAC) Software programmable output range +5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum Operates from single/dual supplies Total unadjusted error (TUE): 0.1% FSR maximum Settling time: 10 μs maximum Integrated reference buffers See data sheet for additional features

Differential Input, Dual, Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC Features: Dual 14-bit SAR ADC Simultaneous sampling Throughput rate: 4.2 MSPS per channel Specified for VDD of 2.5 V Power dissipation: 36 mW at 4.25 MSPS On-chip reference: 2.048 V ± 0.25%, 6 ppm/°C Dual conversion with read High speed serial interface: SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible −40°C to +125°C Y grade operation, −40°C to +85°C B grade operation 16-lead TSSOP and 18-lead LFCSP packages Qualified for automotive applications

Fully Accurate, Quad, 16-Bit, Buffered VOUT, 4.5 V to 5.5 V nanoDAC with SPI Interface Features: Low power quad 12-/14-/16-bit DAC, ±1 LSB INL Pin compatible and performance upgrade to AD5666 Individual and common voltage reference pin options Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale 3 power-down functions and per-channel power-down Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option 14-/16-lead TSSOP Internal reference buffer and internal output amplifier 

Differential/Single-Ended Input, Dual, Simultaneous Sampling, 2 MSPS, 12-Bit, 3-Channel SAR A/D Converter Features: Dual 12-bit, 3-channel ADC Throughput rate: 2 MSPS Specified for VDD of 2.7 V to 5.25 V Power consumption: 9 mW at 1.5 MSPS with 3 V supplies 27 mW at 2 MSPS with 5 V supplies Pin-configurable analog inputs 12-channel single-ended inputs 6-channel fully differential inputs 6-channel pseudo differential inputs 70 dB SNR at 50 kHz input frequency Accurate on-chip reference: 2.5 V ±0.2% maximum @ 25°C, 20 ppm/°C maximum Dual conversion with read 437.5 ns, 32 MHz SCLK High speed serial interface SPI®-/QSPI™-/MICROWIRE&trade-/DSP-compatible −40°C to +125°C operation Shutdown mode: 1 μA maximum 32-lead LFCSP and 32-lead TQFP 1 MSPS version, AD7265

Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC Features: Dual 12-bit SAR ADC Simultaneous Sampling Throughput rate: 5 MSPS per channel Specified for VDD at 2.5 V No conversion latency Power dissipation: 36 mW at 5 MSPS On-chip reference: 2.048 V ± 0.25%, 6ppm/°C Dual conversion with read High speed serial interface: SPI-/QSPI™-/MICROWIRE™-/DSP-compatible −40°C to +125°C operation Available in a 16-lead TSSOP

10-Bit, 4 Oversampling SDTV Video Decoder Features: Automotive versions qualified per AEC-Q100, Grade 1 Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling for Y/C mode, and 2× oversampling for YPrPb (per channel) 3 video input channels with on-chip antialiasing filter CVBS (composite), Y/C (S-video), and YPrPb (component) video input support 5-line adaptive comb filters and CTI/DNR video enhancement Adaptive Digital Line Length Tracking (ADLLT), signal processing, and enhanced FIFO management give mini-TBC functionality See data sheet for additional features