1 kV Dual Channel Digital Isolators (1/1 channel directionality) Features: Narrow-body, RoHS-compliant, 8-lead SOIC Safety and regulatory approvals UL recognition UL 1577: 1000 V rms for 1 minute Low power operation 5 V operation 2.4 mA per channel maximum at 0 Mbps to 1 Mbps 11.8 mA per channel maximum at 25 Mbps 3.3 V operation 1.7 mA per channel maximum at 0 Mbps to 1 Mbps 8.2 mA per channel maximum at 25 Mbps Bidirectional communication Up to 25 Mbps data rate (NRZ) 3 V/5 V level translation High temperature operation: 105°C High common-mode transient immunity: >15 kV/μs

CMOS, 12-Bit Serial DACPORT Features: 12-Bit CMOS DAC with On-Chip Voltage Reference Output Amplifier Three Selectable Output Ranges -5 V to + 5 V, 0 V to +5 V, 0 V to +10 V Serial Interface 300 kHz DAC Update Rate Small Size: 16-Lead DIP or SOIC Nonlinearity: ±1/2 LSB Tmin to Tmax Low Power Dissipation: 100 mW Typical  

25V, 600mA Buck-Boost DC/DC Converter with 1.6A Quiescent Current Features: Regulates VOUT Above, Below or Equal to VIN Wide VIN Range: 2.4V to 25V, <1V to 25V (Using EXTVCC Input) VOUT Range: 1V to 25V Adjustable Output Voltage (LTC3130) Four Selectable Fixed Output Voltages (LTC3130-1) 1.2µA No-Load Input Current in Burst Mode® Operation (VIN = 12V, VOUT = 5V) 600mA Output Current in Buck Mode Pin-Selectable 850mA/450mA Current Limit (LTC3130) Up to 95% Efficiency Pin-Selectable Burst Mode Operation 1.2MHz Ultralow Noise PWM Frequency Accurate RUN Pin Threshold n Power Good Indicator Programmable Maximum Power Point Control IQ = 500nA in Shutdown Thermally-Enhanced 20-Lead 3mm × 4mm QFN and 16-Lead MSOP Packages

6GHz High Linearity I/Q Demodulator with Wideband IF Amplifier Features:300MHz to 6GHz Operating FrequencyWide IF Bandwidth: DC to 1GHz (–1dB Bandwidth)High Mixer IIP3: 30dBm at 1.9GHzHigh Total OIP3: 40dBm at 1.9GHzHigh Total OIP2: 74dBm at 1.9GHzUser Adjustable OIP2 to 80dBmUser Adjustable Image Rejection to 60dBUser Adjustable DC Offset NullSerial InterfacePower Conversion Gain: 7.7dB at 1.9GHz31dB RF Attenuator with 1dB Step SizeRF Switch with 40dB Isolation at 1.9GHzSingle-Ended RF Inputs with On-Chip TransformerIF Amplifier Gain Adjustable in 8 StepsOperating Temperature Range (TC): –40°C to 105°C32-Lead 5mm × 5mm QFN Package

60V Synchronous Buck Multi-Chemistry Battery Charger Features: Wide Input Voltage Range: 4.5V to 60V Wide Battery Voltage Range: 2.4V to 60V Built-In Charge Algorithms for Lead-Acid and Li-Ion ±0.5% Float Voltage Accuracy ±5% Charge Current Accuracy Maximum Power Point Tracking Input Control NTC Temperature Compensated Float Voltage Two Open Drain Status Pins Thermally Enhanced 28-Lead 4mm × 5mm QFN Package

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs  Support for lane rates up to 16 Gbps per lane  1.65 W total power per channel at 3 GSPS (default settings)  Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO  4 cascaded half-band filters  Phase coherent NCO switching Up to 4 channels available  Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

Low Input Bias Current, Wide BW JFET Precision Dual Op Amp Features: Low Noise 6 nV/√Hz Low Offset Voltage: 100 µV Max Low Input Bias Current 10 pA Max Fast Settling: 600 ns to 0.01% Low Distortion Unity Gain Stable No Phase Reversal Dual-Supply Operation: ±5 V to ±13 V