28 V, 200 mA, Low Noise, Linear Regulator Features: Low noise: 18 μV rms Power supply rejection ratio (PSRR): 66 dB at 10 kHz at VOUT = −3 V Positive or negative enable logic Stable with small 2.2 μF ceramic output capacitor Input voltage range: −2.7 V to −28 V Maximum output current: −200 mA Low dropout voltage: −185 mV at −200 mA load Initial accuracy: ±1% Accuracy over line, load, and temperature +2% maximum/−3% minimum Low quiescent current, IGND = −650 μA with −200 mA load Low shutdown current: −2 μA Adjustable output from −1.22 V to −VIN + VDO Current-limit and thermal overload protection 6- and 8-lead LFCSP and 5-lead TSOT Supported by ADIsimPower tool

18 GHz to 44 GHz, GaAs, pHEMT, 32 dBm (>1 W), MMIC Power Amplifier Features:ADPA7005AEHZ Output P1dB: up to 31 dBm typical PSAT: up to 32 dBm typical Gain: up to 15.5 dB typical Output IP3: up to 42.5 dBm typical Supply voltage: 5 V at 1400 mA 50 matched input/output 18-terminal, 7 mm × 7 mm LCC_HS package Integrated power detectorADPA7005CHIP Output P1dB: 31 dBm typical at 20 GHz to 34 GHz PSAT: 32 dBm typical at 20 GHz to 34 GHz Gain: 17 dB typical at 20 GHz to 34 GHz Output IP3: 41 dBm typical at 20 GHz to 34 GHz Supply voltage: 5 V at 1200 mA maximum 50 Ω matched input/output Die size: 3.75 mm × 3.47 mm × 0.1 mm

0.1 GHz to 6 GHz Silicon SP5T Switch Features: Nonreflective 50 Ω design Low insertion loss: 1.5 dB at 4 GHz High isolation: 50 dB at 4 GHz High input linearity 0.1 dB compression (P0.1dB): 34 dBm typical Third-order intercept (IP3): 57 dBm typical High power handling at 85°C 33 dBm through path 27 dBm terminated path ESD rating 3.5 kV HBM, Class 2 Single-supply or dual-supply operation Optional internal negative voltage generator (NVG) 1.8 V logic-compatible control 4 mm × 4 mm, 24-lead LFCSP

5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter Features: Wideband RF output frequency range: 5.9 GHz to 23.6 GHz Two upconversion modes Direct conversion from baseband I/Q to RF Single sideband upconversion from real IF LO input frequency range: 5.4 GHz to 14 GHz LO doubler for up to 28 GHz Matched 100 Ω balanced RF output, LO input, and IF input High impedance baseband inputs Sideband suppression and carrier feedthrough optimization Variable attenuator and power detector for Tx power control Programmable via 4-wire SPI interface 32-lead, 5 mm × 5 mm LFCSP microwave packaging

Integrated Dual RF Receiver Features: Dual receivers Maximum Receiver BW: 200 MHz Fully integrated, fractional-N, RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuneable range: 75 MHz to 6000 MHz

High Performance Fourth Generation DSP Features: 200 MHz core clock speed 2 Mbits of on-chip RAM FIR, IIR, and FFT accelerators Digital Applications Interface (DAI) enabling user-definable access to peripherals including an S/P DIF Tx/Rx, and 8-channel asynchronous sample rate converter Fully enhanced DMA engine including scatter/gather DMA, delay line DMA 8 serial ports (SPORTs) supporting I2S, left-justified sample pair, and TDM modes Watch Dog Timer Shift Registers 2 SPI-compatible ports supporting master and slave modes UART and Two-Wire Interface 16 Pulse Width Modulation (PWM) channels 3 full-featured timers Small footprint, 88-lead LFCSP and 100-Ld LQFP package options Commercial, Industrial, and automotive temperature ranges available

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity

5.7 kV rms, Signal Isolated, Basic CAN FD Transceiver Features: 5.7 kV rms signal isolated CAN FD transceiver 1.7 V to 5.5 V supply and logic side levels 4.5 V to 5.5 V supply on bus side ISO 11898-2:2016-compliant CAN FD Data rates up to 12 Mbps for CAN FD Low maximum loop propagation delay: 150 ns Extended common-mode range: ±25 V Bus fault protection (CANH, CANL): ±40 V Passes EN 55022, Class B by 6 dB Safety and regulatory approvals VDE certificate of conformity, VDE V 0884-10 (pending) UL: 5700 V rms for 1-minute duration per UL 1577 (pending) CSA component acceptance 5A at 5.7 kV rms IEC 60950, IEC 61010 (pending) High common-mode transient immunity: >75 kV/µs Industrial operating temperature range: −40°C to +125°CADM3050E-EP Supports defense and aerospace applications (AQEC standard) Download ADM3050E-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19605 DSCC Drawing Number