3 nV /Hz, Low Power Instrumentation Amplifier Features: Low power 2.3 mA maximum supply current Low noise 3.2 nV/√Hz maximum input voltage noise at 1 kHz 200 fA/√Hz current noise at 1 kHz Excellent ac specifications  10 MHz bandwidth (G = 1) 2 MHz bandwidth (G = 100) 0.6 µs settling time to 0.001% (G = 10) 80 dB CMRR to 20 kHz (G = 1) 35 V/µs slew rate High precision dc performance (AD8421BRZ) 94 dB CMRR minimum (G = 1) 0.2 μV/C maximum input offset voltage drift 1 ppm/C maximum gain drift (G = 1)500 pA maximum input bias current Inputs protected to 40 V from opposite supply ±2.5 V to 18 V dual supply (5 V to 36 V single supply) Gain set with a single resistor (G = 1 to 10,000) Available in 8-lead LFCSP, 8-lead MSOP, and 8-lead SOIC Download AD8421-KGD Data Sheet Available As Known Good Die and fully guaranteed to data sheet specificationsAD8421-EP supports defense and aerospace applications (AQEC standard) Download AD8421-EP data sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/13625 DSCC Drawing Number

60 MHz, 2000 V/s, Monolithic Op Amp with Quad Low Noise Features: Wide bandwidth 60 MHz at gain of −1  33 MHz at gain of −10  Slew rate: 2000 V/μs  20 MHz full power bandwidth, 20 V p-p, RL = 500 Ω  Fast settling: 100 ns to 0.1% (10 V step) Differential gain error: 0.03% at 4.4 MHz  Differential phase error: 0.16° at 4.4 MHz  Low offset voltage: 150 μV maximum (B Grade) Low quiescent current: 6.5 mA  Available in tape and reel in accordance with EIA-481-A standard

Digitally Programmable Sensor Signal Amplifier with EMI Filters Features: EMI filters at input pins Specified from −40°C to +140°C Low offset voltage: 10 μV maximum Low input offset voltage drift: 65 nV/°C maximum High CMRR: 94 dB minimum Digitally programmable gain and output offset voltage Programmable output clamp voltage Open and short wire fault detection Low-pass filtering Single-wire serial interface Stable with any capacitive load SOIC_N and LFCSP_VQ packages 4.5 V to 5.5 V operation

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

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I/O EXPANDER, 8BIT, 400KHZ, LFCSP-24; Chip Configuration: 8bit; Bus Frequency: 400kHz; IC Interface Type: I2C; Supply Voltage Min: 1.65V; Supply Voltage Max: 3.6V; Interface Case Style: LFCSP; No. of Pins: 24Pins; No. of I/O's: 18I/O's; Product Range: ADP5587 Series; Automotive Qualification Standard: -; RoHS Phthalates Compliant: Yes; MSL: MSL 3 - 168 hours; SVHC: No SVHC (07-Jul-2017)

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