High Speed Industrial CAN Transceiver with Bus Protection for 24 V Systems Features: Physical layer CAN transceiver 5 V operation on VCC Complies with ISO 11898 standard High speed data rates up to 1 Mbps Short-circuit protection on CANH and CANL against shorts to power/ground in 24 V systems Unpowered nodes do not disturb the bus Connect 110 or more nodes on the bus Slope control for reduced EMI Thermal shutdown protection Low current standby mode Industrial operating temperature range (−40°C to +125°C) Available in 8-lead SOIC package

3.0 V to 5.5 V with VIO, 12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver Features: TIA/EIA RS-485 compliant over full supply range 3.0 V to 5.5 V operating voltage range on VCC 1.62 V to 5.5 V VIO logic supply option available ESD protection on the bus pins IEC 61000-4-2 ±12 kV contact discharge IEC 61000-4-2 ≥ ±12 kV air discharge HBM: ≥ ±30 kV Full hot swap support (glitch free power-up/power-down) High speed 50 Mbps data rate (ADM3065E/ADM3066E/ADM3067E/ADM3068E) Low speed 500 kbps data rate for long cables (ADM3061E/ADM3062E/ADM3063E) Full receiver short-circuit, open circuit, and bus idle fail-safe Extended temperature range up to 125°C PROFIBUS compliant at VCC ≥ 4.5 V Half duplex and full duplex models available Allows connection of up to 128 transceivers onto the bus Space-saving package options 10-lead, 3 mm × 3 mm LFCSP 8-lead and 10-lead, 3 mm × 3 mm MSOP 8-lead and 14-lead, narrow body SOIC

3.0 V to 5.5 V with VIO, 12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver Features: TIA/EIA RS-485 compliant over full supply range 3.0 V to 5.5 V operating voltage range on VCC 1.62 V to 5.5 V VIO logic supply option available ESD protection on the bus pins IEC 61000-4-2 ±12 kV contact discharge IEC 61000-4-2 ≥ ±12 kV air discharge HBM: ≥ ±30 kV Full hot swap support (glitch free power-up/power-down) High speed 50 Mbps data rate (ADM3065E/ADM3066E/ADM3067E/ADM3068E) Low speed 500 kbps data rate for long cables (ADM3061E/ADM3062E/ADM3063E) Full receiver short-circuit, open circuit, and bus idle fail-safe Extended temperature range up to 125°C PROFIBUS compliant at VCC ≥ 4.5 V Half duplex and full duplex models available Allows connection of up to 128 transceivers onto the bus Space-saving package options 10-lead, 3 mm × 3 mm LFCSP 8-lead and 10-lead, 3 mm × 3 mm MSOP 8-lead and 14-lead, narrow body SOIC

3-V, RS-232 Serial Port Driver-Receiver Features: Green Idle power-saving mode Single 2.7 V to 3.6 V power supply Operates with 3 V logic 0.1 µF to 1 µF charge pump capacitors Low EMI Low power shutdown: 20 nA Full RS-232 compliance 460 kb/s data rate One receiver active in shutdown (ADM3307E/ADM3311E/ADM3312E/ADM3315E) Two receivers active in shutdown (ADM3310E) ESD >15 kV IEC 1000-4-2 on RS-232 I/Os ESD >15 kV IEC 1000-4-2 on CMOS and RS-232 I/Os (ADM3307E) Qualified for automotive applications

6.5 V, 1 A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO Features: Input voltage range: 2.3 V to 6.5 V Maximum load current: 1 A Low noise: 5 μV rms independent of output voltage at 100 Hz to 100 kHz Fast transient response: 1.5 μs for 1 mA to 500 mA load step 60 dB PSRR at 100 kHz Low dropout voltage: 42 mV at 500 mA load, VOUT = 3 V Initial accuracy: −0.5% (minimum), +1% (maximum) Accuracy over line, load, and temperature: ±1.5% Quiescent current, IGND = 0.7 mA with no load Low shutdown current: 0.25 μA at VIN = 5 V Stable with small 4.7 μF ceramic output capacitor Adjustable and fixed output voltage options: 1.2 V to 5.0 V Adjustable output from 1.2 V to VIN − VDO Precision enable Adjustable soft start 8-lead, 3 mm × 3 mm LFCSP package Supported by ADIsimPower tool

Ultralow Power Voltage Detector with Disable Input and Low Threshold Voltages Features: Ultralow power consumption with ICC = 92 nA (typical) Precision, low voltage monitoring Pretrimmed voltage monitoring threshold options 20 options from 0.5 V to 1.9 V ±1.3% threshold accuracy over full temperature range Output disable input 23 µs to 26 µs typical propagation delay Open-drain type output Power supply glitch immunity Available in a 1.46 mm × 0.96 mm WLCSP Operational temperature range: −40°C to +85°C

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity

12-Bit, 210 MSPS TxDAC D/A Converter Features: High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR at 5 MHz output, 125 MSPS: 70 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V Reference CMOS compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP Edge-triggered latches

4T2R Direct RF Transmitter and Observation Receiver Features: Flexible reconfigurable radio common platform design Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R) RFDAC/RFADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RFCLK input option Versatile digital features Configurable digital up/down conversion (DDC and DUC) 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent 48-bit NCO per DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Auxiliary features Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins supporting different user configurations ADC clock driver with selectable divide ratios TDD power savings option and sharing ADCs SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes per each DAC and ADC JESD204B compatible with maximum 15.5 Gbps lane rate JESD204C compatible with maximum 24.75 Gbps lane rate Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

4T4R Direct RF Receiver and Transmitter Features: Flexible, reconfigurable radio common platform design Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) RF DAC/RF ADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RF clock input option Versatile digital features Selectable interpolation and decimation filters Configurable DDCs and DUCs 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC) FDUCs and FDDCs are fully bypassable 2 independent 48-bit NCOs per DUC or DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Supports real or complex digital data (8-, 12-, or 16-bit) Auxiliary features ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins support toggling between modes TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) Supports Subclass 1 Supports multidevice synchronization 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch