The 10 clock outputs of the AD9544 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.The AD9544 is available in a 48-lead LFCSP (7 mm ? 7 mm) package and operates over the ?40?C to +85?C temperature range.Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.Appliations SyncE and GPS synchronization and jitter cleanup Optical transport networks (OTN), SDH, and macro and small cell base stations OTN mapping/demapping with jitter cleaning Small base station clocking, including baseband and radio Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking Cable infrastructures Carrier Ethernet

VCO Oscillators VCO SMT w/Buffer amp, 2.6 - 2.8 GHz

Data Conversion IC Development Tools EVAL-ADAS1000

Supervisory Circuits Cascadable Super Sequencer w/ Margin con

ANAAD8224HBCPZ-WP

The AD9516-5?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO/VCXO of up to 2.4 GHz.The AD9516-5 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit otherapplications with demanding phase noise and jitter requirements.The AD9516-5 features six LVPECL outputs (in three pairs)and four LVDS outputs (in two pairs). Each LVDS output canbe reconfigured as two CMOS outputs. The LVPECL outputsoperate to 1.6 GHz, the LVDS outputs operate to 800 MHz, andthe CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division forthe LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allowa range of divisions up to a maximum of 1024.The AD9516-5 is available in a 64-lead LFCSP and can beoperated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V (nominal).The AD9516-5 is specified for operation over the industrial range of ?40?C to +85?C.For applications requiring an integrated EEPROM, or needing additional outputs, the AD9520-5?and AD9522-5?are available.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

The SSM2141 is an integrated differential amplifier intended to receive balanced line inputs in audio applications requiring a high level of noise immunity and optimum common-mode rejection. The SSM2141 typically achieves 100 dB of common-mode rejection (CMR), whereas implementing an op amp with four off-the-shelf precision resistors will typically achieve only 40 dB of CMR-inadequate for high-performance audio.The SSM2141 achieves low distortion performance by maintaining a large slew rate of 9.5 V/µs and high open-loop gain. Distortion is less than 0.002% over the full audio bandwidth. The SSM2141 complements the SSM2142 balanced line driver. Together, these devices comprise a fully integrated solution for equivalent transformer balancing of audio signals without the problems of distortion, EMI fields, and high cost.Additional applications for the SSM2141 include summing signals, differential preamplifiers, and 600 Ohm low distortion buffer amplifiers. For similar performance with G = 1/2, see SSM2143.APPLICATIONS Line Receivers Summing Amplifiers Buffer Amplifiers–Drives 600 Ω Load

DC1322A: Demo Board for LT3751 High Voltage Capacitor Charger Controller with Regulation

The ADSP-BF512 is the low cost entry point into the Blackfin Processor family. It offers an optimal balance between performance, peripheral integration, and price and is well suited for the most cost-sensitive applications including portable test equipment, embedded modems, biometrics, and consumer audio. The high performance 16/32-bit Blackfin embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the dynamic power management (DPM) functionality allow system designers a flexible platform to address a wide range of applications.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF512 provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.

Demonstration circuit 2350B features the LTC6813-1, 18-channel battery-stack monitor. Multiple boards can be linked through a 2-wire isolated serial interface (isoSPI™) to monitor a long series of cells in a stack. The DC2350B demo board also features reversible isoSPI enabling a redundant communication path. The PCB, components, and DuraClik connectors are optimized for low EMI susceptibility and emissions. The DC2350B can communicate to a PC by connecting a DC2792B dual master isoSPI together with DC2026C Linduino® One. The DC2026 must be loaded with the appropriate program (called a sketch) to control the battery-stack monitor IC and receive data through a USB serial port. The DC2026 provides a standard SPI interface which can be translated to isoSPI and then connected to a DC2350B isoSPI port (J4 or J5 connector). The DC2792B companion board provides two SPI-isoSPI channels for reversible operation.