Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

0.25 dB LSB, 7-Bit, Silicon Digital Attenuator, 0.1 GHz to 6.0 GHz Features: Attenuation range: 0.25 dB LSB steps to 31.75 dB Low insertion loss: 1.1 dB at 1.0 GHz 1.3 dB at 2.0 GHz Typical step error: less than ±0.1 dB Excellent attenuation accuracy: less than ±0.2 dB Low phase shift error: 6° phase shift at 1.0 GHz Safe state transitions High linearity 1 dB compression (P1dB): 31 dBm typical Input third-order intercept (IP3): 54 dBm typical RF settling time (0.05 dB final RF output): 250 ns Single supply operation: 3.3 V to 5.0 V ESD rating: Class 2 (2 kV human body model (HBM)) 24-lead, 4 mm × 4 mm LFCSP package: 16 mm2

Microwave Wideband Synthesizer with Integrated VCO Features: RF output frequency range: 62.5 MHz to 16,000 MHz Fractional-N synthesizer and integer-N synthesizer High resolution 39-bit fractional modulus Typical spurious fPFD: −90 dBc Integrated rms jitter: 38 fs (1 kHz to 100 MHz) Normalized phase noise floor: −234 dBc/Hz fPFD operation to 250 MHz Reference input frequency operation to 600 MHz Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output 62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x 8,000 MHz to 16,000 MHz output at RF16x Lock time approximately 3 ms with automatic calibration Lock time <30 μs with autocalibration bypassed, typical Analog and digital power supplies: 3.3 V typical VCO supply voltage: 3.3 V and 5 V RF output mute function 7mm × 7mm, 48-terminal LGA package

Microwave Wideband Synthesizer with Integrated VCO Features: Output frequency range: 800 MHz to 12.8 GHz Jitter = 18 fsRMS (Integration BW: 100 Hz to 100 MHz) Jitter = 27 fsRMS (ADC SNR Method) Wideband Noise Floor: -160 dBc/Hz @12 GHz PLL Specifications: -239 dBc/Hz: Normalized In-Band Phase Noise Floor -147 dBc/Hz: Normalized In-Band 1/f Noise Phase Detector Frequency up to 500 MHzReference Input Frequency up to 1 GHz Typical -100 dBc PFD spursReference to Output Delay Specifications: Part-to-Part Standard Deviation: 3 ps Temperature Drift: 0.03 ps/ Adjustment Step Size: <+/-0.1 ps Multi-chip Output Phase Alignment 3.3 V and 5 V Power supplies 7 mm x 7 mm 48 Lead LGA

Single Channel, 256-Position, I2C / SPI, Nonvolatile Digital Potentiometer Features: 10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 μs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 3 mm × 3 mm LFCSP Qualified for automotive applications

Nonvolatile, Quad, 64-Position Digital Potentiometer Features: Nonvolatile Memory Preset Maintains Wiper Settings 4-channel independent programmable 64-position resolution EEMEM restore time: 140 μs typical Full monotonic operation 10 kΩ, 50 kΩ, and 100 kΩ terminal resistance See Data Sheet for Additional Information

2.5 V to 5.5 V, 500 A, 2-Wire Interface Quad Voltage Output 12-Bit DAC in a 10-Lead MicroSOIC Package Features: AD5305: 4 buffered 8-bit DACs in 10-lead MSOP A version: ±1 LSB INL, B version: ±0.625 LSB INL AD5315: 4 buffered 10-bit DACs in 10-lead MSOP A version: ±4 LSB INL, B version: ±2.5 LSB INL AD5325: 4 buffered 12-bit DACs in 10-lead MSOP A version: ±16 LSB INL, B version: ±10 LSB INL 2-wire (I2C®-compatible) serial interface 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 80 nA @ 3 V, 200 nA @ 5 V  Low power operation: 500 μA @ 3 V, 600 μA @ 5 V Three power-down modes Double-buffered input logic Output range: 0 V to VREF Power-on reset to 0 V Simultaneous update of outputs (LDAC function) Software clear facility Data readback facility On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C 

High Bandwidth 12-Bit Parallel Interface Multiplying D/A Converter Features: 2.5 V to 5.5 V supply operation Fast parallel interface (17 ns write cycle) Update rate of 20.4 MSPS INL of ±1 LSB for 12-bit DAC ±10 V reference input 10 MHz multiplying bandwidth Extended temperature range: –40°C to +125°C See data sheet for additional features

Quad, 16-Bit nanoDAC with 5ppm/C On-Chip Reference Features: Low power, smallest pin-compatible, quad nanoDACs  AD5664R: 16 bits AD5644R: 14 bits AD5624R: 12 bits User selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD; and 12-ball, 1.665 mm × 2.245 mm WLCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface, up to 50 MHz

16-Channel, 12-/16-BitnanoDAC+ with 2 ppm/C VoltageReference Temperature Coefficient, SPI Interface Features: High performance High relative accuracy (INL): ±4 LSB maximum at 16 bits (AD5679/AD5679R) TUE: ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Low drift, 2.5 V voltage reference temperature coefficient: 2 ppm/°C typical 40 mA short-circuit current Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply range Simplified implementation User selectable gain of 1 or 2 (GAIN pin) 1.8 V logic compatibility 50 MHz serial peripheral interface (SPI) with readback or daisy chain 28-lead, 4 mm × 4 mm, RoHS compliant LFCSP