Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs  Support for lane rates up to 16 Gbps per lane  1.65 W total power per channel at 3 GSPS (default settings)  Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO  4 cascaded half-band filters  Phase coherent NCO switching Up to 4 channels available  Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

16-Channel, 16-Bit, Serial Input, Voltage-Output DAC Features: 16-channel DAC in 52-lead LQFP package Guaranteed monotonic to 16/14 bits Nominal output voltage range of −10 V to +10 V Multiple output spans available Temperature monitoring function Channel monitoring multiplexer Digital reset (RESET) See Data Sheet for Additional Information

16-Channel, 14-Bit, Serial Input, Voltage-Output DAC Features: 16-channel DAC in 52-lead LQFP package Guaranteed monotonic to 16/14 bits Nominal output voltage range of −10 V to +10 V Multiple output spans available Temperature monitoring function Channel monitoring multiplexer Digital reset (RESET) Clear function to user-defined SIGGNDx GPIO function System calibration function allowing user-programmable offset and gain Channel grouping and addressing features Data error checking feature SPI-compatible serial interface 2.5 V to 5.5 V digital interface Simultaneous update of DAC outputs

Single Channel, 16-Bit, Current Source & Voltage Output DAC, HART Connectivity Features: 16-bit resolution and monotonicity Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA ±0.01% FSR typical total unadjusted error (TUE) ±3 ppm FSR/°C output drift Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V 10% overrange ±0.01% FSR typical TUE ±2 ppm FSR/°C output drift Flexible serial digital interface On-chip output fault detection On-chip reference: 10 ppm/°C maximum Optional regulated DVCC output Asynchronous clear function Power supply range AVDD: 10.8 V to 40 V AVSS: −26.4 V to −3 V/0 V Current loop compliance voltage: AVDD – 2.5 V Temperature range: −40°C to +105°C TSSOP and LFCSP packages

Single Channel, 16-Bit Current/Voltage Output DAC with HART Connectivity Features: 16-bit resolution and monotonicity Current or voltage output available on a single terminal Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, 0 mA to 24 mA, ±20 mA, ±24 mA, and −1 mA to +22 mA Voltage output ranges (with 20% overrange): 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V User programmable offset and gain Advanced on-chip diagnostics, including a 12-bit ADC On-chip reference −40°C to +115°C temperature range 32-Lead, 5 mm × 5 mm LFCSP package

8-Channel, 12-Bit, Configurable ADC/DAC with On-Chip Reference, I2C Interface Features: 8-channel, configurable ADC/DAC/GPIO Configurable as any combination of 8 12-bit DAC channels 8 12-bit ADC channels 8 general-purpose I/O pins Integrated temperature sensor 16-lead TSSOP and LFCSP and 16-ball WLCSP packages I2C interface

Single, 16-Bit nanoDAC with 5 ppm/C On-Chip Reference Features: Low power, single nanoDAC AD5660: 16 bits 12-Bit Accuracy Guaranteed On-chip, 1.25 V/2.5 V, 5 ppm/°C reference Tiny 8-lead SOT-23/MSOP packages Power-down to 480 nA @ 5 V, 200 nA @ 3 V 3 V/5 V single power supply Guaranteed 16-bit monotonic by design Power-on reset to zero/midscale 3 power-down functions Serial interface with Schmitt-triggered inputs Rail-to-rail operation SYNC interrupt facility

16-Channel, 12-/16-Bit nanoDAC+ with 2 ppm/C Voltage Reference TC, I2C Interface Features: High relative accuracy (INL): ±4 LSB maximum at 16 bits (AD5677R only) TUE: ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Low drift, 2.5 V voltage reference TC: 2 ppm/°C typical 40 mA short-circuit current Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply range Simplified implementation User selectable gain of 1 or 2 (GAIN pin) 1.8 V logic compatibility 400 kHz I2C-compatible serial interface 28-lead, 4 mm × 4 mm, RoHS compliant LFCSP