Single-Supply, Low Power, Precision FET Input Quad Buffer Features: Low power 250 μA maximum supply current per amplifier FET input 2 pA maximum input bias current at 25°C Extremely high input impedance Low noise 13 nV/√Hz voltage noise at 1 kHz 0.4 μV p-p voltage noise (0.1 Hz to 10 Hz) 0.8 fA/√Hz current noise at 1 kHz High dc precision 3 μV/°C maximum offset drift (B grade) 3 MHz bandwidth Unique pinout No leakage from inputs to supply pins Provides guarding capability Rail-to-rail output Single-supply operation Input range extends to ground Wide supply range Single-supply: 3 V to 36 V Dual-supply: ±1.5 V to ±18 V  Available in a compact 10-lead MSOP

10 MHz, G = 1, 10, 100, 1000 iCMOS Programmable Gain Instrumentation Amplifier Features: Small package: 10-lead MSOP Programmable gains: 1, 10, 100, 1000 Digital or pin-programmable gain setting Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 100 dB (minimum), G = 100 Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.2 µV/°C (maximum), G = 1000 See data sheet for additional features

Fast, Voltage-Out, DC to 440 MHz, 95 dB Logarithmic Amplifier Features: Multistage demodulating logarithmic amplifier Voltage output, rise time <15 ns High current capacity: 25 mA into grounded RL 95 dB dynamic range: –91 dBV to +4 dBV Single supply of 2.7 V min at 8 mA typ DC to 440 MHz operation, ±0.4 dB linearity Slope of +24 mV/dB, intercept of –108 dBV Highly stable scaling over temperature Fully differential dc-coupled signal path 100 ns power-up time, 1 mA sleep current

RF Vector Modulator 1.5 GHz TO 2.4 GHz Features: Cartesian amplitude and phase modulation 1.5 GHz to 2.4 GHz frequency range Continuous magnitude control of −4.5 dB to −34.5 dB Continuous phase control of 0° to 360° Output third-order intercept 17.5 dBm Output 1 dB compression point 8.5 dBm Output noise floor −150.5 dBm/Hz at full gain Adjustable modulation bandwidth up to 230 MHz Fast output power disable 4.75 V to 5.25 V single-supply voltage 

3 nV /Hz, Low Power Instrumentation Amplifier Features: Low power 2.3 mA maximum supply current Low noise 3.2 nV/√Hz maximum input voltage noise at 1 kHz 200 fA/√Hz current noise at 1 kHz Excellent ac specifications  10 MHz bandwidth (G = 1) 2 MHz bandwidth (G = 100) 0.6 µs settling time to 0.001% (G = 10) 80 dB CMRR to 20 kHz (G = 1) 35 V/µs slew rate High precision dc performance (AD8421BRZ) 94 dB CMRR minimum (G = 1) 0.2 μV/C maximum input offset voltage drift 1 ppm/C maximum gain drift (G = 1)500 pA maximum input bias current Inputs protected to 40 V from opposite supply ±2.5 V to 18 V dual supply (5 V to 36 V single supply) Gain set with a single resistor (G = 1 to 10,000) Available in 8-lead LFCSP, 8-lead MSOP, and 8-lead SOIC Download AD8421-KGD Data Sheet Available As Known Good Die and fully guaranteed to data sheet specificationsAD8421-EP supports defense and aerospace applications (AQEC standard) Download AD8421-EP data sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/13625 DSCC Drawing Number

60 MHz, 2000 V/s, Monolithic Op Amp with Quad Low Noise Features: Wide bandwidth 60 MHz at gain of −1  33 MHz at gain of −10  Slew rate: 2000 V/μs  20 MHz full power bandwidth, 20 V p-p, RL = 500 Ω  Fast settling: 100 ns to 0.1% (10 V step) Differential gain error: 0.03% at 4.4 MHz  Differential phase error: 0.16° at 4.4 MHz  Low offset voltage: 150 μV maximum (B Grade) Low quiescent current: 6.5 mA  Available in tape and reel in accordance with EIA-481-A standard

Digitally Programmable Sensor Signal Amplifier with EMI Filters Features: EMI filters at input pins Specified from −40°C to +140°C Low offset voltage: 10 μV maximum Low input offset voltage drift: 65 nV/°C maximum High CMRR: 94 dB minimum Digitally programmable gain and output offset voltage Programmable output clamp voltage Open and short wire fault detection Low-pass filtering Single-wire serial interface Stable with any capacitive load SOIC_N and LFCSP_VQ packages 4.5 V to 5.5 V operation

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

8-Bit, 1 GSPS, JESD204B, Quad Analog-to-Digital Converter Features:JESD204B (Subclass 1 and Subclass 0) coded serial digital outputs Lane rates up to 15 Gbps 1.6 W total power at 1 GSPS 400 mW per ADC channel SFDR: 71 dBFS at 611 MHz (1.44 V p-p input range) SNR: 48.6 dBFS at 611 MHz (1.44 V p-p input range) SINAD: 48.5 dBFS at 611 MHz (1.44 V p-p input range) 0.9 V, 1.8 V, and 2.5 V dc supply operation No missing codes Internal ADC voltage reference Analog input buffer On-chip dithering to improve small signal linearityFlexible differential input range 1.44 V p-p to 2.16 V p-p (1.44 V p-p default) 1.4 GHz analog input full power bandwidth Fast detect bits for efficient AGC implementation Differential clock input Integer clock divide by 1, 2, 4, or 8 On-chip temperature diode Flexible JESD204B lane configurations

4T2R Direct RF Transmitter and Observation Receiver Features: Flexible reconfigurable radio common platform design Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R) RFDAC/RFADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RFCLK input option Versatile digital features Configurable digital up/down conversion (DDC and DUC) 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent 48-bit NCO per DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Auxiliary features Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins supporting different user configurations ADC clock driver with selectable divide ratios TDD power savings option and sharing ADCs SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes per each DAC and ADC JESD204B compatible with maximum 15.5 Gbps lane rate JESD204C compatible with maximum 24.75 Gbps lane rate Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch