200 g Range, 3-Axis Digital Accelerometer Features: ±200 g measurement range Low power: 170 μA in measurement mode and 17 μA in standby mode at VS = 2.5 V (typical) User selectable bandwidth up to 3200 Hz ODR Fixed 13-bit output resolution Supply voltage range: 2.0 V to 3.6 V Embedded memory management system with FIFO technology minimizes host processor load Shock event detection Activity/inactivity monitoring SPI (3- or 4-wire) and I2C digital interfaces Wide temperature range: −40 to +125°C 10,000 g shock survival Pb free and RoHS compliant Small and thin: 32-lead, 5 mm × 5 mm × 1.45 mm LFCSP AEC-Q100 qualified for automotive applications

Dual 12-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface Features: Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of full-scale range (FSR) maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range

8-Channel, 24-Bit, Simultaneous Sampling ADC Features: 8-channel, 24-bit simultaneous sampling ADC Single-ended or true differential inputs PGA per channel (gains of 1, 2, 4, and 8) Low dc input current ±4 nA (differential)/±8 nA (single-ended) Up to 128 kSPS ODR per channel Programmable ODRs and bandwidth SRC for coherent sampling Sampling rate resolution up to 15.2 × 10−6 SPS Low latency sinc3 and sinc5 filter paths Adjustable phase synchronization Internal 2.5 V reference Two power modes High resolution mode Low power mode Optimizes power dissipation and performance Low resolution SAR ADC for system and chip diagnostics Power supply Bipolar (±1.65 V) or unipolar (3.3 V) supplies Digital I/O supply: 1.8 V to 3.6 V Performance temperature range: −40°C to +105°C Functional temperature range: −40°C to +125°C Performance Combined ac and dc performance 107 dB SNR/dynamic range at 32 kSPS in high resolution mode (sinc5) −109 dB THD ±8 ppm of FSR INL ±15 μV offset error ±0.1% FS gain error ±10 ppm/°C typical temperature coefficient

Dual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface Features: Dual 12-Bit, 2-Channel ADC Fast Throughput Rate 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low Power: 11.4 mW Max at 1 MSPS with 3 V Supplies 24 mW Max at 1 MSPS with 5 V Supplies Wide Input Bandwidth 70 dB SNR at 300 kHz Input Frequency Onboard Reference 2.5 V Flexible Power/Throughput Rate Management Simultaneous Conversion/Read No Pipeline Delays High-Speed Serial Interface SPI®/QSPI™/ MICROWIRE™/DSP Compatible Shut-Down Mode: µA Max 20-Lead TSSOP Package

16-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common range High common-mode rejection Single-ended to differential conversion 2.048 V input range with 4.096 V REFBUF Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball BGA package 4× footprint reduction versus discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL: 0.4 LSB typical, 1 LSB maximum SINAD: 89 dB typical at 1 kHz THD: 115 dB at 1 kHz, 106 dB at 400 kHz Gain error: 0.005% FS typical Gain error drift: 1 ppm/C maximum On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: 40C to +85C

18-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common-mode voltage range High common-mode rejection Single-ended to differential conversion Pin selectable input range with overrange Input ranges with 4.096 V REFBUF: ±10 V, ±5 V, ±4.096 V, ±2.5 V, and ±1.5 V Gain/attenuation options: 0.37, 0.73, 0.87, 1.38, and 2.25 Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball CSP_BGA package 2.5× footprint reduction vs. discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL error: ±3.1 ppm typical, ±6.2 ppm maximum (Gain = 0.73, gain = 0.87, gain = 1.38, gain = 2.25) SINAD: 90.4 dB typical at 20 kHz (gain = 0.73) THD: −117 dB at 1 kHz, −110 dB at 100 kHz (gain = 0.73) Gain error: ±0.005%FS typical Gain error drift: ±0.13 ppm/°C typical On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: −40°C to +85°C

SigmaDSP Compact Digital Audio Processor with Extended Internal Memory Features: Qualified for automotive applications High performance SigmaDSP core enables low latency and audio applications Active Noise Cancellation (ANC) Echo-Canceller and Noise Reduction (ECNR) Surround sound algorithms Features SigmaStudio, a proprietary graphical Integrated Development Environment (IDE), for the development of custom signal flows Comprehensive Toolbox of pre-defined building blocks Faster design time with proven solutions Intuitive system design 294.912 MHz, 32-bit SigmaDSP core at 1.2 V 24 kWords of program memory 80 kWords of parameter/data RAM 6144 SIMD instructions per sample at 48 kHz 1600 ms digital audio delay pool at 48 kHz Audio I/O and routing 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital I/O up to a sample rate of 192 kHz Flexible configuration of I2S, left and right justified, and up to 16-channel TDM formats on serial data pins 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and 139 dB dynamic range Stereo S/PDIF input and output at 192 kHz Four PDM microphone input channels Multichannel, byte addressable TDM serial ports Clock oscillator for generating master clock from crystal Integer PLL and flexible clock generators Integrated die temperature sensor I2C and SPI control interfaces (both slave and master) Standalone operation Self-boot from serial EEPROM 6-channel, 10-bit SAR auxiliary control ADC 14 multipurpose pins for digital controls and outputs On-chip regulator for generating 1.2 V from 1.8 V to 3.3 V supply 72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm exposed pad Temperature range: −40°C to +105°C

Three ADCs, One DAC, Low Power Codec with Audio DSPs Features: Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing Tensilica HiFi 3z DSP core Quad MAC per cycle: 24 x 24-bit multiplier and 64-bit accumulator Flexible power operation mode: 24.576 MHz, 49.152 MHz, 73.728 MHz, and 98.304 MHz 336 kB total memory JTAG debug and trace Low latency, 24-bit ADCs and DAC 106 dB SNR (signal through ADC with A-weighted filter) 110 dB combined SNR (signal through DAC and headphone with A-weighted filter) Programmable double precision MAC engine for maximum 24-stage equalizer Serial port sample rates from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 3 differential or single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs Analog differential audio output, configurable as either line output or headphone drive 2 PDM output channels PLL supporting any input clock rate from 30 kHz to 36 MHz 4 channel asynchronous sample rate converters (ASRCs) 2, 16-channel serial audio ports supporting I2S, left justified, right justified, or up to TDM16 (TDM12 in Turbo mode) 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.85 V to 1.21 V Headphone HPVDD at 1.8 V typical Headphone HPVDD_L at 1.2 V to HPVDD Control/communication interfaces I2C, SPI, or UART control ports Master quad SPI (QSPI) UART communication port Self-boot from QSPI flash Flexible GPIO and IRQ 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP

Ultrafast SiGe Voltage Comparator (Featuring Reduced Swing PECL Output Drivers) Features: 180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) −2 V to +3 V input range with +5 V/−5 V supplies On-chip terminations at both input pins Resistor-programmable hysteresis Differential latch control Power supply rejection > 70 dB

High Performance Polyphase Energy Measurement IC Features: 7 high performance analog-to-digital converters (ADCs) 101 dB signal-to-noise ratio (SNR) 10,000:1 dynamic range Wide input range: ±1 V, 0.707 V rms full scale Differential inputs ±25 ppm/°C maximum channel temperature drift (including ADC, internal VREF, and PGA drift) enabling Class 0.2 meters with standard external components Power quality measurements Line frequency: 1 measurement per phase Zero crossing detection, zero-crossing timeout Phase angle measurements Supports current transformers (CTs) and Rogowski coil (di/dt) sensors Multiple range phase/gain compensation for CTs Digital integrator for Rogowski coils Flexible waveform buffer Able to resample waveform to ensure 64 points per line cycle for ease of external harmonic analysis Events can trigger waveform storage Simplifies data collection for IEC 61000-4-7 harmonic analysis Advanced metrology feature set Total active power, volt-amperes reactive (VAR), volt-amperes (VA), watthour, VAR-hour, and VA-hour Fundamental VAR and VAR-hour Current and voltage rms per phase (xIRMS, xVRMS) Supports active energy standards: IEC 62053-21, IEC 62053-22; EN50470-3; OIML R46, ANSI C12.20 Supports reactive energy standards: IEC 62053-23, IEC 62053-4 High speed communication port 10 MHz serial peripheral interface (SPI)