14-Bit, 80Msps Ultra-Low Power 1.8V ADCs Features: 73.4dB SNR 85dB SFDR Low Power: 127mW/106mW/89mW Single 1.8V Supply CMOS, DDR CMOS or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full-Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package

12-Bit, 105Msps Ultralow Power 1.8V ADCs Features: 70.8dB SNR 85dB SFDR Low Power: 124mW/103mW/87mW Single 1.8V Supply CMOS, DDR CMOS or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full-Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package

12-Bit, 1 GSPS/500 MSPS JESD204B,Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs 1.5 W total power per channel at 1 GSPS (default settings) SFDR 79 dBFS at 340 MHz (1 GSPS) 85 dBFS at 340 MHz (500 MSPS) SNR 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS, 1 GSPS) 65.6 dBFS at 340 MHz (AIN = −1.0 dBFS, 500 MSPS) ENOB = 10.4 bits at 10 MHz (1 GSPS) DNL = ±0.16 LSB; INL = ±0.35 LSB (1 GSPS) Noise density −151 dBFS/Hz (1 GSPS) −150 dBFS/Hz (500 MSPS) 1.25 V, 2.5 V, and 3.3 V dc supply operation Low swing full-scale input 1.34 V p-p typical (1 GSPS) 1.63 V p-p typical (500 MSPS) No missing codes Internal ADC voltage reference Flexible termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 2 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation Differential clock input Optional decimate by 2 DDC per channel Differential clock input Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither

14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B Subclass 0 or Subclass 1 coded serial digital outputs Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and 250 MSPS Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS Total power consumption: 711 mW at 250 MSPS 1.8 V supply voltages Integer 1-to-8 input clock divider Sample rates of up to 250 MSPS IF sampling frequencies of up to 400 MHz Internal analog-to-digital converter (ADC) voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS) 95 dB channel isolation/crosstalk Serial port control Energy saving power-down modes

16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC Features: SNR: 83 dB (85 dBFS) to 10 MHz input SFDR: 87 dBc to 10 MHz input Noise figure: 15 dB Input impedance: 1 kΩ Power: 600 mW 1.8 V analog supply operation 1.8 V to 3.3 V output supply Selectable bandwidth 2.5 MHz/5 MHz/10 MHz real 5 MHz/10 MHz/20 MHz complex Output data rate: 30 MSPS to 160 MSPS See data sheet for additional features

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) See data sheet for additional features

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 109 mW per channel at 12 bits/40 MSPS (TGC) 70 mW per channel in CW Doppler Flexible power-down modes Overload recovery in <10 ns See data sheet for additional features

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 109 mW per channel at 12 bits/40 MSPS (TGC) 70 mW per channel in CW Doppler Flexible power-down modes Overload recovery in <10 ns See data sheet for additional features

12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO Features: Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.4 GHz to 1.8 GHz Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Automatic/manual reference holdover and reference switchover modes, with revertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 1.6 GHz LVPECL outputs divided into 4 groups Each group of 3 outputs shares a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs < 16 ps Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz) Automatic synchronization of all outputs on power-up Manual output synchronization available SPI- and I2C-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings

Low Jitter, DDS-based Clock Generator and Synthesizer Features: Excellent intrinsic jitter performance 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable) Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable) 8 programmable phase/frequency profiles 400 MSPS internal DDS clock speed 48-bit frequency tuning word resolution 14-bit programmable phase offset 1.8 V supply for device operation 3.3 V supply for I/O, CML driver, and charge pump output Software controlled power-down 48-lead LFCSP package Programmable charge pump current (up to 4 mA) Dual-mode PLL lock detect 655 MHz CML-mode PECL-compliant output driver