Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2+ Line Driver Features: Four current feedback, high current amplifiers Ideal for use as ADSL/ADSL2+ dual-channel central office (CO) line drivers Low power operation Power supply operation from ±5 V (+10 V) up to ±12 V (+24 V) Less than 3 mA/amp quiescent supply current for full power ADSL/ADSL2+ CO applications (20.4 dBm line power, 5.5 CF) Three active power modes plus shutdown High output voltage and current drive 500 mA peak output drive current 42.6 V p-p differential output voltage Low distortion −93 dBc at1 MHz second harmonic −103 dBc at 1 MHz third harmonic High speed: 515 V/μs differential slew rate Additional functionality of AD8392AACP On-chip, common-mode voltage generation

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) See data sheet for additional features

8-Bit, 50 MSPS/80 MSPS/100 MSPS ADC Features: Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth 46.5 dB SNR at 100 MSPS with 41 MHz input 1 Vp-p Analog Input Range Single +3.0 V Supply Operation (2.7 -3.6 V) Power Down Mode: 4.2 mW

Ethernet/Gigabit Ethernet Clock Generator Features: Redundant input reference clock capability Reference monitoring function Fully integrated VCO/PLL core Jitter (rms) 0.234 ps rms jitter (10 kHz to 10 MHz) at 156.25 MHz 0.243 ps rms jitter (12 kHz to 20 MHz) at 156.25 MHz Input frequency: 19.44 MHz or 25 MHz Preset frequency translations Using a 19.44 MHz input reference 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz Using a 25 MHz input reference 25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 80 MHz, 100 MHz, 125 MHz, 133.3 MHz, 156.25 MHz, 160 MHz, 312.5 MHz Output drive formats: HSTL, LVDS, HCSL, and 1.8 V and 3.3 V CMOS Integrated loop filter (requires a single external capacitor) 2 copies of reference clock output Device configuration via strapping pins (PPRx) Space-saving 7 mm × 7 mm 48-lead LFCSP 3.3 V operation

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Features: 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply SNR 82 dBFS at 30 MHz input and 105 MSPS data rate 83 dBFS at 9.7 MHz input and 25 MSPS data rate SFDR 90 dBc at 30 MHz input and 105 MSPS data rate 95 dBc at 9.7 MHz input and 25 MSPS data rate Low power 328 mW per channel at 105 MSPS 119 mW per channel at 25 MSPS Integer 1-to-8 input clock divider See data sheet for additional featuresAD9650-EP supports defense and aerospace applications (AQEC standard) Download AD9650-EP data sheet (pdf)

3.0 V to 5.5 V, 12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver Features: TIA/EIA RS-485 compliant over full supply range 3.0 V to 5.5 V operating voltage range on VCC 1.62 V to 5.5 V VIO logic supply option available ESD protection on the bus pins IEC 61000-4-2 ±12 kV contact discharge IEC 61000-4-2 ≥ ±12 kV air discharge HBM: ≥ ±30 kV Full hot swap support (glitch free power-up/power-down) High speed 50 Mbps data rate (ADM3065E/ADM3066E/ADM3067E/ADM3068E) Low speed 500 kbps data rate for long cables (ADM3061E/ADM3062E/ADM3063E) Full receiver short-circuit, open circuit, and bus idle fail-safe Extended temperature range up to 125°C PROFIBUS compliant at VCC ≥ 4.5 V Half duplex and full duplex models available Allows connection of up to 128 transceivers onto the bus Space-saving package options 10-lead, 3 mm × 3 mm LFCSP 8-lead and 10-lead, 3 mm × 3 mm MSOP 8-lead and 14-lead, narrow body SOIC

Complete 12-Bit CMOS Multiplying DAC Features: 12-Bit CMOS MDAC with Output Amplifier 4-Quadrant Multiplication Low Power LC2MOS Guaranteed Monotonic (Tmin to Tmax) Space-Saving 0.3' DIPS and 24- or 28- Terminal Surface Mount Packages Application Resistors On Chip for Gain Ranging, etc.

Complete 12-Bit CMOS Multiplying DAC Features: 12-Bit CMOS MDAC with Output Amplifier 4-Quadrant Multiplication Low Power LC2MOS Guaranteed Monotonic (Tmin to Tmax) Space-Saving 0.3' DIPS and 24- or 28- Terminal Surface Mount Packages Application Resistors On Chip for Gain Ranging, etc.