Ultralow Noise, 200 mA, Linear Regulator Features: PSRR performance of 54 dB at 100 kHz Ultralow noise independent of VOUT 3 μV rms, 0.1 Hz to 10 Hz 9.5 μV rms, 0.1 Hz to 100 kHz 9 µV rms, 10Hz to 100KHz 17 µV rms, 10Hz to 1MHz Low dropout voltage: 150 mV at 200 mA load Maximum output current: 200 mA Input voltage range: 2.2 V to 5.5 V Low quiescent and shutdown current Initial accuracy: ±1% Accuracy over line, load, and temperature: −2.5%/+1.5% 5-lead TSOT package and 6-lead LFCSP package

6.5 V, 500 mA, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO Features: Input voltage range: 2.3 V to 6.5 V Maximum load current: 500 mA Low noise: 5 μV rms independent of output voltage at 100 Hz to 100 kHz Fast transient response: 1.5 μs for 1 mA to 500 mA load step 60 dB PSRR at 100 kHz Low dropout voltage: 42 mV at 500 mA load, VOUT = 3 V Initial accuracy: ±0.75% Accuracy over line, load, and temperature: ±1.25% Quiescent current, IGND = 0.7 mA at no load Low shutdown current: 0.25 μA at VIN = 5 V Stable with small 4.7 μF ceramic output capacitor Adjustable and fixed output voltage options: 1.2 V to 5.0 V Adjustable output from 1.2 V to VIN − VDO Precision enable Adjustable soft start 8-lead, 3 mm × 3 mm LFCSP package Supported by ADIsimPower tool

Microprocessors Supervisory Circuit in 4-Lead SOT-143, Logic Low RESET Bar Output Features: Superior upgrade for MAX811/MAX812 Specified over temperature Low power consumption: 5 μA typical Precision voltage monitor: 2.5 V, 3 V, 3.3 V, 5 V options Reset assertion down to 1 VCC Power-on reset: 140 ms minimum Logic low RESET output Built-in manual reset

Microprocessor Supervisory Circuit with Watchdog Feature, 4.65V Threshold Voltage, Low Supply Current and Active Low Reset Output. Upgrade for ADM699 Features: Superior Upgrade for ADM698/ADM699, MAX698/MAX699 Guaranteed RESET Assertion with VCC = 1 V Low 70 µA Supply Current Precision 4.65 V Voltage Monitor Power OK/Reset Time Delay Power OK/Reset Time Delay Watchdog Timer Minimum Component Count Performance Specified over Temperature ADM8698 is obsolete

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) See data sheet for additional features

8-Bit, 50 MSPS/80 MSPS/100 MSPS ADC Features: Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth 46.5 dB SNR at 100 MSPS with 41 MHz input 1 Vp-p Analog Input Range Single +3.0 V Supply Operation (2.7 -3.6 V) Power Down Mode: 4.2 mW

Ethernet/Gigabit Ethernet Clock Generator Features: Redundant input reference clock capability Reference monitoring function Fully integrated VCO/PLL core Jitter (rms) 0.234 ps rms jitter (10 kHz to 10 MHz) at 156.25 MHz 0.243 ps rms jitter (12 kHz to 20 MHz) at 156.25 MHz Input frequency: 19.44 MHz or 25 MHz Preset frequency translations Using a 19.44 MHz input reference 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz Using a 25 MHz input reference 25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 80 MHz, 100 MHz, 125 MHz, 133.3 MHz, 156.25 MHz, 160 MHz, 312.5 MHz Output drive formats: HSTL, LVDS, HCSL, and 1.8 V and 3.3 V CMOS Integrated loop filter (requires a single external capacitor) 2 copies of reference clock output Device configuration via strapping pins (PPRx) Space-saving 7 mm × 7 mm 48-lead LFCSP 3.3 V operation

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Features: 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply SNR 82 dBFS at 30 MHz input and 105 MSPS data rate 83 dBFS at 9.7 MHz input and 25 MSPS data rate SFDR 90 dBc at 30 MHz input and 105 MSPS data rate 95 dBc at 9.7 MHz input and 25 MSPS data rate Low power 328 mW per channel at 105 MSPS 119 mW per channel at 25 MSPS Integer 1-to-8 input clock divider See data sheet for additional featuresAD9650-EP supports defense and aerospace applications (AQEC standard) Download AD9650-EP data sheet (pdf)