RF Amplifier IC General Purpose 4.8GHz ~ 6GHz 16-QFN (3x3)

The AD4003/AD4007/AD4011 are high accuracy, high speed, low power, 18-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage. The AD4003/AD4007/AD4011 power scales linearly with throughput. Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2 in the data sheet).Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin and eliminating the need for external protection diodes. Fast device throughput up to 2 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input and output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by using the separate VIO logic supply.APPLICATIONS Automated test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems Instrumentation and control systems

The ADN4620/ADN4621 are dual-channel, signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 2.5 Gbps with very low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide drop-in galvanic isolation of LVDS signal chains. AC coupling and/or level shifting to the LVDS receivers and from the LVDS drivers allows isolation of other high speed signals, such as current mode logic (CML).The ADN4620/ADN4621 include a refresh mechanism to monitor the input and output states and ensure that they remain the same in the absence of data transitions (for example, at power-on). For lower power consumption and high speed operation with low jitter, the isolator circuits rely on 1.8 V supplies, while 3.3 V supplies are used for LVDS receivers to support the full common-mode range with an input voltage range (input common mode plus differential input voltage) of 0 V to 2.4 V per Table 2 in the data sheet.The devices are fully specified over a wide industrial temperature range and are available in a compact SSOP package with 5.3 mm creepage (for reinforced insulation at ac mains voltages).APPLICATIONS Analog front-end isolation Data plane isolation Isolated high speed clock and data links Multigigabit serialization/deserialization (SERDES) PCB-to-PCB optical replacement (for example, short reach fiber)Protected by U.S. Patents 7,075,329; 9,941,565; and 10,205,442. Other patents are pending.

Clock & Timer Development Tools LTC6994-2 Demo Board 100ms, Output Rising Edge Delayed from Trigger Rising Edge

Demonstration circuit 873 features the LTC1867L Octal 16-bit ADC. The LTC1867L can be software programmed for a unipolar 0 to 2.5V or bipolar ±1.25V input range. The 8 channel multiplexer can be programmed for 8 single-ended inputs with respect to ground, 7 single-ended inputs with respect to the COM/CH7 pin, 4 differential inputs, or any combination of these.

The ADN4624 is a quad-channel, signal isolated, low voltage differential signaling (LVDS) buffer that operates at up to 2.5 Gbps with very low jitter. The device integrates Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide drop-in galvanic isolation of LVDS signal chains. AC coupling and/or level shifting to the LVDS receivers and from the LVDS drivers allows isolation of other high speed signals such as current mode logic (CML).The ADN4624 includes a refresh mechanism to monitor the input and output states and ensure they remain the same in the absence of data transitions (for example, at power-on).For lower power consumption and high speed operation with low jitter, the LVDS and isolator circuits rely on 1.8 V supplies. The ADN4624 is fully specified over a wide industrial temperature range and is available in a 28-lead, wide-body, finer pitch SOIC_W_FP package with 8.3 mm creepage and clearance (for 5.7 kV rms or 8 kVPEAK surge and impulse voltages and reinforced insulation at ac mains voltages) or 6 mm ? 6 mm LFCSP package with 1.27 mm creepage and clearance (for basic/functional isolation).APPLICATIONS Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links Multi-gigabit serialization/deserialization (SERDES) Board-to-board optical replacement (for example, short reach fiber)

Demonstration circuit 1780A-A features PolyPhase® design using the LTM4620EV, the high efficiency, high density, dual 13A, switch mode step-down power module regulator. The input voltage is from 4.5V to 16V. The output voltage is jumper selectable from 1.0V to 2.5V. DC1780A-A can deliver nominal 50A output current with 2× LTM4620s in parallel. As explained in the data sheet, output current derating is necessary for certain VIN, VOUT, and thermal conditions.

The ADA4927 is a low noise, ultralow distortion, high speed, current feedback differential amplifier that is an ideal choice for driving high performance ADCs with resolutions up to 16 bits from dc to 100 MHz. The output common-mode level can easily be matched to the required ADC input common-mode levels. The internal common-mode feedback loop provides exceptional output balance and suppression of even-order distortion products.Differential gain configurations are easily realized using an external feedback network comprising four resistors. The current feedback architecture provides loop gain that is nearly independent of closed-loop gain, achieving wide bandwidth, low distortion, and low noise at higher gains and lower power consumption than comparable voltage feedback amplifiers.The ADA4927 is fabricated using the Analog Devices, Inc., silicon-germanium complementary bipolar process, enabling very low levels of distortion with an input voltage noise of only 1.3 nV/√Hz. The low dc offset and excellent dynamic performance of the ADA4927 make it well suited for a wide variety of data acquisition and signal processing applications.The ADA4927-1 is available in a Pb-free, 3 mm × 3 mm 16-lead LFCSP, and the ADA4927-2 is available in a Pb-free, 4 mm × 4 mm 24-lead LFCSP. The pinouts are optimized to facilitate printed circuit board (PCB) layout and to minimize distortion. They are specified to operate over the −40°C to +105°C temperature range.Applications ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Differential line drivers

The ADF5610 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference source. The wideband microwave voltage controlled oscillator (VCO) design permits frequency operation from 7300 MHz to 14600 MHz at a single radio frequency (RF) output. A series of frequency dividers with a differential frequency output allows operation from 57 MHz to 14600 MHz. Analog and digital power supplies for the PLL circuitry range from 3.1 V to 3.5 V, and the VCO supplies are between 4.75 V and 5.25 V. The charge pump supply voltage can be extended up to 3.6 V for improved frequency band overlap and extended upper frequency range.The ADF5610 has an integrated VCO with a fundamental frequency of 3650 MHz to 7300 MHz. These frequencies are internally doubled and routed to the RFOUT pin. An additional differential output allows the doubled VCO frequency to be divided by 1, 2, 4, 8, 16, 32, 64, or 128, allowing the user to generate RF output frequencies as low as 57 MHz. A simple 3?wire serial port interface (SPI) provides control of all on-chip registers. To conserve power, this divider block can be disabled when not needed through the SPI interface. Likewise, the output power for both the single-ended output and the differential output are programmable via the VCO register settings. The ADF5610 also contains various power-down modes for the VCO circuitry and PLL circuitry.The integrated phase detector (PD) and delta-sigma (?-?) modulator, capable of operating at up to 100 MHz, permit wide loop bandwidths and fast frequency tuning with a typical spurious level of ?100 dBc.With phase noise levels from ?115 dBc/Hz at 7.3 GHz to ?109 dBc/Hz at 14.6 GHz, the ADF5610 is equipped to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. The low phase noise floor eliminates any contribution to modulator and mixer noise floor in transmitter applications.The ADF5610 is a PLL with integrated VCO. The device features an innovative programmable performance technology that enables the ADF5610 to tailor current consumption and corresponding noise performance to individual applications by selecting either a low current consumption mode or a high performance mode for improved phase noise performance.Additional features of the ADF5610 include approximately 3 dBof RFOUT gain control in 1.5 dB steps and 5 dB of control onthe differential port in approximately 2.5 dB steps. Finally, the ?-?modulator with exact frequency mode enables users to generateoutput frequencies with 0 Hz frequency error.APPLICATIONSMilitary and defenseTest equipmentClock generationWireless infrastructureSatellite and very small aperture terminal (VSAT)Microwave radio

Data Conversion IC Development Tools LTC2208IUP-14 LVDS OUT, 130Msps, 14-Bit ADC 70MHz < Ain < 140MHz, (req. DC890 & LVDS_XFMR)