20 MHz to 6 GHz RF/IF Gain Block, Fixed Gain of 15 dB Features: Fixed gain of 15 dB  Operation up to 6 GHz  Input/output internally matched to 50 Ω  Integrated bias control circuit  Output IP3 44 dBm at 500 MHz 40 dBm at 900 MHz  Output 1 dB compression: 19.7 dBm at 900 MHz  Noise figure of 3.5 dB at 900 MHz  Single 5 V power supply  Small footprint 8-lead LFCSP  Pin compatible with 20 dB gain ADL5542  1 kV ESD (Class 1C) 

Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC Features: Serial data input: 10 Mbps to 2.7 Gbps Exceeds ITU-T jitter specifications Integrated limiting amplifier 5 mV p-p sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Proprietary dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Integrated PRBS generator and detector No reference clock required Loss of lock indicator Supports double data rate BERMON or sample phase adjust options Rate selectivity without the use of a reference clock I2C interface to access optional features Single-supply operation: 3.3 V Low power 650 mW (ADN2817) 600 mW (ADN2818) 5 mm × 5 mm 32-lead LFCSP

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