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|
Texas Instruments
LMR23630FDRRR
|
Texas Instruments
SN65LVDS250DBTG4
|
Texas Instruments
SN65LVDS180DG4
|
Texas Instruments
SN65LVDS049PWG4
|
Texas Instruments
SN65LVDS048APWG4
|
Texas Instruments
HPA00022DGGR
|
Texas Instruments
HPA00394ZQLR
|
Texas Instruments
HPA00441ZALR
|
Texas Instruments
INA826SIDRCT
|
Texas Instruments
TPS2547RTER
|
| Price |
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| RoHS |
|
Y |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
| Lead Status |
|
See ti.com |
No |
No |
No |
No |
No |
No |
No |
No |
No |
| Package Group |
|
SO PowerPAD,SON |
TSSOP |
|
|
|
TSSOP,VQFN |
BGA MICROSTAR JUNIOR |
|
VSON |
WQFN |
| Switching Frequency(Min)(kHz) |
|
200 |
|
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| Vin(Min)(V) |
|
4.5 |
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|
4.5 |
| Control Mode |
|
Current Mode |
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| Rating |
|
Catalog |
Catalog |
|
|
|
Catalog |
Catalog |
|
Catalog |
Catalog |
| Operating Temperature Range(C) |
|
-40 to 125 |
-40 to 85 |
|
|
|
0 to 70 |
-40 to 85 |
|
-40 to 125 |
-40 to 115 |
| Vin(Max)(V) |
|
36 |
|
|
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|
5.5 |
| Type |
|
Converter |
|
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| Regulated Outputs(#) |
|
1 |
|
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| Vout(Min)(V) |
|
1 |
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| Vout(Max)(V) |
|
30 |
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| Special Features |
|
Enable,Frequency Synchronization,Light Load Efficiency,Pre-Bias Start-Up,Synchronous Rectification,UVLO Adjustable |
|
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| Approx. Price (US$) |
|
1.40 | 1ku |
7.09 | 1ku |
|
|
|
3.29 | 1ku |
3.60 | 1ku |
|
|
0.95 | 1ku |
| Duty Cycle(Max)(%) |
|
97 |
|
|
|
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|
|
|
|
|
| Iq(Typ)(mA) |
|
0.075 |
|
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|
0.2 |
|
| Iout(Max)(A) |
|
3 |
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| Switching Frequency(Max)(kHz) |
|
2200 |
|
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| Output Signal |
|
|
LVDS |
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| Input Signal |
|
|
CML,LVDS,LVPECL |
|
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| Package Size |
|
|
mm2 |
|
|
|
mm2 |
mm2 |
|
mm2 |
mm2 |
| Function |
|
|
Crosspoint |
|
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|
DDR Register |
DDR2 PLL |
|
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| No. of Tx |
|
|
4 |
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| No. of Rx |
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|
4 |
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| Signaling Rate(Mbps) |
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|
2000 |
|
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| ESD HBM(kV) |
|
|
3 |
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| ICC(Max)(mA) |
|
|
145 |
|
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| Number of Outputs |
|
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|
26 |
10 |
|
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| VCC(V) |
|
|
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|
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|
2.5 |
1.8 |
|
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|
| Operating Frequency Range(Max)(MHz) |
|
|
|
|
|
|
200 |
410 |
|
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|
| Output Drive(mA) |
|
|
|
|
|
|
20 |
9 |
|
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| Operating Frequency Range(Min)(MHz) |
|
|
|
|
|
|
0 |
125 |
|
|
|
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter)(ps) |
|
|
|
|
|
|
N/A |
30 |
|
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| tsk(o)(ps) |
|
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|
N/A |
30 |
|
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| t(phase error)(ps) |
|
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|
N/A |
35 |
|
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| Vs(Max)(V) |
|
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|
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|
36 |
|
| CMRR(Min)(dB) |
|
|
|
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|
|
|
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|
120 |
|
| Bandwidth at Min Gain(Typ)(MHz) |
|
|
|
|
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|
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|
1 |
|
| Input Offset (+/-)(Max)(uV) |
|
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|
150 |
|
| Vs(Min)(V) |
|
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3 |
|
| Gain Non-Linearity (+/-)(Max)(%) |
|
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|
0.0005 |
|
| Gain(Min)(V/V) |
|
|
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|
1 |
|
| Input Bias Current (+/-)(Max)(nA) |
|
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|
65 |
|
| Input Offset Drift (+/-)(Max)(uV/C) |
|
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|
2 |
|
| Number of Channels(#) |
|
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|
1 |
|
| Gain(Max)(V/V) |
|
|
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|
1000 |
|
| Gain Error (+/-)(Max)(%) |
|
|
|
|
|
|
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|
0.15 |
|
| Noise at 0.1 Hz - 10 Hz(Typ)(uVpp) |
|
|
|
|
|
|
|
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|
0.52 |
|
| Noise at 1kHz(Typ)(nV/rt(Hz)) |
|
|
|
|
|
|
|
|
|
18 |
|
| Current Limit(A) |
|
|
|
|
|
|
|
|
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|
0.2 to 3.0 |
| rDS(on) per FET(Typ)(mOhms) |
|
|
|
|
|
|
|
|
|
|
73 |
| Number of Switches |
|
|
|
|
|
|
|
|
|
|
1 |
| Fault Response |
|
|
|
|
|
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|
|
|
Retry |
| Current Limit Accuracy @ 1A |
|
|
|
|
|
|
|
|
|
|
+/-10% |
| Enable |
|
|
|
|
|
|
|
|
|
|
Active High |
| Continuous Current(Max)(A) |
|
|
|
|
|
|
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|
3.0 |
