The ADL5303 is a monolithic logarithmic detector optimized for the measurement of low frequency signal power in fiberoptic systems and offers a large dynamic range in a versatile andeasily used form. Wide measurement range and accuracy are achieved using proprietary design and precise laser trimming.The ADL5303 requires only a single positive supply, VPS, of 5 V. When using low supply voltages, the log slope can be altered tofit the available span. Low quiescent current and chip disablefacilitate use in battery-operated applications.The input current, IPD, flows in the collector of an optimally scaled NPN transistor, connected in a feedback path around alow offset JFET amplifier. The current summing input nodeoperates at a constant voltage, independent of current, with a default value of 0.5 V; this may be adjusted over a wide range. An adaptive biasing scheme is provided for reducing photo-diode dark current at very low light input levels. The VPDB pin applies approximately 0.1 V reverse bias across the photodiode for IPD = 100 pA, rising linearly to 2.0 V of reverse bias at IPD = 10 mA to improve response time at higher power levels. The input pin INPT is flanked by the VSUM guard pins that track the voltage at the summing node. Connecting the exposed pad of the device to the VSUM pins provides a continuous guard to minimize leakage into the INPT pin.The default value of the logarithmic slope at the VLOG output is set by an internal 5 k? resistor. Logarithmic slope can belowered with an external shunt resistor or increased using the buffer and a pair of external feedback resistors. The addition of a capacitor at the VLOG pin provides a simple low-pass filter.The intermediate voltage, VLOG, is buffered in an output stage that can swing to within about 100 mV of ground and the positive supply, VPS, and provides a peak current drive capacity of ?20 mA. An on-board 2 V reference is provided to facilitate the repositioning of the intercept. The incremental bandwidth of a translinear logarithmic amplifier inherently diminishes for small input currents. At IPD =1 nA, the bandwidth of the ADL5303 is approximately 2 kHz increasing in proportion to IPD up to a maximum value of 10 MHz.APPLICATIONS High accuracy optical power measurement Wide range baseband log compression Versatile detector for APC loops

Demonstration circuit 2362A is an adjustable 3A linear regulator featuring the LT3033. The LT3033 is a very low dropout voltage (VLDO™) linear regulator that operates from a single input supply down to 0.95V. The device supplies 3A output current with 95mV typical dropout voltage. The LT3033 is ideal for low input voltage to low output voltage applications, providing comparable electrical efficiency to a switching regulator. The LT3033 optimizes stability and transient response with low ESR ceramic output capacitors as small as 10µF. A 10nF bypass capacitor at REF/BYP pin typically reduces output voltage noise to 60µVRMS in a 10Hz to 100kHz bandwidth. Soft-start time is directly proportional to the REF/BYP capacitor value. The LT3033’s current limit, accurate to ±12% over a wide input voltage and temperature range, can be programmed by a single resistor. When the input-to-output differential voltage exceeds 5V, foldback current limit lowers the internal current limit level, which may override the external programmable current limit. LT3033 has a PWRGD pin which indicates when the ADJ pin is within 8% of its nominal value. By connecting an external pull-up resistor from PWRGD to either the IN or OUT pin, PWRGD is pulled low when the output falls below 90.1% of the regulated voltage. As the output voltage rises above 92% of its regulated voltage, the PWRGD pin voltage is pulled up. The LT3033 features output current monitoring by connecting a resistor from the IMON pin to GND. The IMON pin is the collector of a PNP current mirror that outputs 1/2650th of the power PNP current. This circuitry is active for VIMON ≤ (VOUT – 400mV). The LT3033 also features shutdown, reverse-battery protection, thermal limiting with hysteresis and reverse current protection. The LT3033 is available as an adjustable device with an output voltage down to the 200mV reference. The device is available in a thermally enhanced, low profile 3mm × 4mm × 0.75mm QFN package. The LT3033 data sheet gives a complete description of the part, operation and application information. The data sheet must be read in conjunction with this quick start guide for demo circuit 2362A.

The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs.The HMC7043 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components in a base transceiver station (BTS) system, such as data converters, local oscillators, transmit/receive modules, field programmable gate arrays (FPGAs), and digital front-end ASICs. The HMC7043 can generate up to seven DCLK and SYSREF clock pairs per the JESD204B/JESD204C interface requirements.The system designer can generate a lower number of DCLK and SYSREF pairs, and configure the remaining output signal paths for independent phase and frequency. Both the DCLK and SYSREF clock outputs can be configured to support different signaling standards, including CML, LVDS, LVPECL, and LVCMOS, and different bias conditions to adjust for varying board insertion losses. One of the unique features of the HMC7043 is the independent flexible phase management of each of the 14 channels. All 14 channels feature both frequency and phase adjustment. The outputs can also be programmed for 50 ? or 100 ? internal and external termination options. The HMC7043 device features an RF SYNC feature that synchronizes multiple HMC7043 devices deterministically, that is, ensures that all clock outputs start with the same edge. This operation is achieved by rephrasing the nested HMC7043 or SYSREF control unit/divider, deterministically, and then restarting the output dividers with this new phase. The HMC7043 is offered in a 48-lead, 7 mm ? 7 mm LFCSP package with an exposed pad connected to ground. Applications JESD204B/JESD204C clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Phase array reference distribution Microwave baseband cards

The ADAQ4001 is a ?Module? precision data acquisition (DAQ), signal chain solution that reduces the development cycle of a precision measurement system by transferring the signal chain design challenge of component selection, optimization, and layout from the designer to the device. Using system-in-package (SIP) technology, the ADAQ4001 reduces end system component count by combining multiple common signal processing and conditioning blocks into a single device. These blocks include a high resolution 16-bit, 2 MSPS successive approximation register (SAR), analog-to-digital converter (ADC), a low noise, fully differential ADC driver amplifier (FDA), and a stable reference buffer. Using Analog Devices, Inc., iPassives? technology, the ADAQ4001 also incorporates crucial passive components with superior matching and drift characteristics to minimize temperature dependent error sources and to offer optimized performance (see Figure 1 in the data sheet). Housing this signal chain solution in a small, 7 mm ? 7 mm, 0.80 mm pitch, 49-ball CSP_BGA enables compact form factor designs without sacrificing performance and simplifies end system bill of materials management. This level of system integration makes the ADAQ4001 much less sensitive to printed circuit board (PCB) layout while still providing flexibility to adapt to a wide range of signal levels. The serial peripheral interface (SPI)-compatible, serial user interface is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using a separate VIO supply. Specified operation of the ADAQ4001 is from ?40?C to +125?C.APPLICATIONSAutomatic test equipmentMachine automationProcess controlsMedical instrumentationDigital control loops

Demonstration Circuit 2375A is a dual output 350mA step down charge pump with a post-regulator LDO and watchdog timer featuring the LTC3256EMSE. The LTC3256 operates with a wide input voltage range from 5.5V to 38V and is engineered for diagnostic coverage in ISO262262 systems. The LTC3256 can provide up to 350mA of output current from a 12V battery with 2W less power dissipation than 2 ideal linear regulators. The DC2375A was populated with automotive grade components for evaluation. Because of the wide input operating range it is possible to exceed the specified operating junction temperature and even reach thermal shutdown with heavy loads. Please refer to the data sheet for additional information on the thermal limitations of the device.

The ADIS16475 is a precision, miniature MEMS inertial measurement unit (IMU) that includes a triaxial gyroscope and a triaxial accelerometer. Each inertial sensor in the ADIS16475 combines with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, linear acceleration (gyroscope bias), and point of percussion (accelerometer location). As a result, each sensor has dynamic compensation formulas that provide accurate sensor measurements over a broad set of conditions.The ADIS16475 provides a simple, cost effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. The serial peripheral interface (SPI) and register structure provide a simple interface for data collection andconfiguration control.The ADIS16475 is available in a 44-ball, ball grid array (BGA) package that is approximately 11 mm ? 15 mm ? 11 mm.Applications Navigation, stabilization, and instrumentation Unmanned and autonomous vehicles Smart agriculture and construction machinery Factory/industrial automation, robotics Virtual/augmented reality Internet of Moving Things

DC1620A-I: Demo Board for LTC2143-14 14-Bit, 80Msps Low Power Dual ADCs.

The ADCLK954 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 ? on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs.The ADCLK954 features 12 full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias Vcc to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.The output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differential output swing of 1.6 V.The ADCLK954 is available in a 40-lead LFCSP and specified for operation over the standard industrial temperature range of ?40?C to +85?C.APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation

The AD736 is a low power, precision, monolithic true rms-to-dc converter. It is laser trimmed to provide a maximum error of ?0.3 mV ? 0.3% of reading with sine wave inputs. Furthermore, it maintains high accuracy while measuring a wide range of input waveforms, including variable duty-cycle pulses and triac (phase)-controlled sine waves. The low cost and small size of this converter make it suitable for upgrading the performance of non-rms precision rectifiers in many applications. Compared to these circuits, the AD736 offers higher accuracy at an equal or lower cost.The AD736 can compute the rms value of both ac and dc input voltages. It can also be operated as an ac-coupled device by adding one external capacitor. In this mode, the AD736 can resolve input signal levels of 100 ?V rms or less, despite variations in temperature or supply voltage. High accuracy is also maintained for input waveforms with crest factors of 1 to 3. In addition, crest factors as high as 5 can be measured (introducing only 2.5% additional error) at the 200 mV full-scale input level.The AD736 has its own output buffer amplifier, thereby pro-viding a great deal of design flexibility. Requiring only 200 ?A of power supply current, the AD736 is optimized for use in portable multimeters and other battery-powered applications.The AD736 allows the choice of two signal input terminals: a high impedance FET input (1012 ?) that directly interfaces with High-Z input attenuators and a low impedance input (8 k?) that allows the measurement of 300 mV input levels while operating from the minimum power supply voltage of +2.8 V, ?3.2 V. The two inputs can be used either single ended or differentially.The AD736 has a 1% reading error bandwidth that exceeds 10 kHz for the input amplitudes from 20 mV rms to 200 mV rms while consuming only 1 mW.The AD736 is available in four performance grades. The AD736J and AD736K grades are rated over the 0?C to +70?C and ?20?C to +85?C commercial temperature ranges. The AD736A and AD736B grades are rated over the ?40?C to +85?C industrial temperature range. The AD736 is available in three low cost, 8-lead packages: PDIP, SOIC, and CERDIP.PRODUCT HIGHLIGHTS The AD736 is capable of computing the average rectified value, absolute value, or true rms value of various input signals. Only one external component, an averaging capacitor, is required for the AD736 to perform true rms measurement. The low power consumption of 1 mW makes the AD736 suitable for many battery-powered applications. A high input impedance of 1012 ? eliminates the need for an external buffer when interfacing with input attenuators. A low impedance input is available for those applications that require an input signal up to 300 mV rms operating from low power supply voltages.

The ADCLK946 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has a differential input equipped with center-tapped, differential, 100 ? on-chip termination resistors. The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs.The ADCLK946 features six full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.The ECL output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differen-tial output swing of 1.6 V.The ADCLK946 is available in a 24-lead LFCSP and is specified for operation over the standard industrial temperature range of ?40?C to +85?C.ApplicationsLow jitter clock distributionClock and data signal restorationLevel translationWireless communicationsWired communicationsMedical and industrial imagingATE and high performance instrumentation