Demonstration circuit EVAL-LT8692S-AZ is an ultracompact 4 rail power supply featuring the LT8692S, a 42V quad monolithic synchronous step-down Silent Switcher®. The demo circuit is designed for 5V, 3.3V, 1.8V, and 1.2V outputs from a nominal 12V input. The 3.3V, 1.8V and 1.2V converters are powered from the high voltage buck regulator with 5V output, which is powered from a wide range of 6.2V to 42V input. The current capability is 2A for the channel 1, and 1A for the low voltage channels. Internal soft-start, individual current limit, independent enable for each channel simplify the complex design of quad-output power converters. All regulators can be synchronized to a common external clock input or internal oscillator of 2MHz. The table in the demo manual summarizes the performance of the demo board at room temperature. The circuit can be easily modified for different applications. The LT8692S data sheet gives a complete description of the part, operation and application information. The data sheet must be read in conjunction with the quick start guide for demo circuit EVAL-LT8692S-AZ.

DC929A-B: Demo Board for the LTC4089 USB Power Manager with High Voltage Switching Charger.

The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended outputbuffer amplifier, matched to a 50 ? load up to 10 GHz.The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning.The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband waveform generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the mostdemanding high speed ultrawideband RF transmit applications. The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power.The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter.In 2? nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz.In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2? NRZ mode.In baseband modes, such as return-to-zero (RZ) and 1? NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2? NRZ mode.The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones.The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns.The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm ? 15 mm, 0.8 mm pitch BGA_ED package.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz. Fully supports zero IF and other dc-coupled applications. Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter.Applications Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators Electronic warfare: radars, jammers Broadband communications systems Local oscillator drivers1 Protected by U.S. Patents 6,842,132 and 7,796,971.

DC1324A: Demo Board for LTC3672B-2 - Monolithic Fixed-Output 400mA Buck Regulator with Dual 150mA LDOs in 2mm × 2mm DFN

The AD1030 is an analog front end (AFE) that includes a high precision analog-to-digital converter (ADC), voltage output digital-to-analog converters (VDACs), current output digital-to-analog converters (IDACs), thermoelectric cooler (TEC) controller, and analog comparators.The ADC signal chain contains two analog comparator channels, 10 external voltage inputs, VDAC voltage and current monitor channels, IDAC voltage and current monitor channels, a precharge buffer, and a 1 MSPS successive approximation register (SAR) ADC.The AD1030 provides four IDAC channels. These are low noise, low drift current sources with programmable full-scale output ranges (50 mA, 100 mA, or 150 mA). Each IDAC channel has 12-bit resolution.There are 9?, 12-bit VDAC outputs. Four of these VDACs (Channel 0 to Channel 3) support either a positive voltage range of 0 V to 2.5 V or a negative range from 0 V to ?2.5 V. These ranges can be extended to 0 V to AVDD and 0 V to AVDDNEG.Channel 4 to Channel 7 of the VDACs support a positive voltage range of 0 V to 2.5 V. VDAC Channel 8 supports a positive voltage range of 0 V to 2.5 V. Optionally, Channel 4 to Channel 7 of the VDACs can support an output range of 0 V to AVDD.The AD1030 also integrates a TEC controller with a heating and cooling current up to 1.3 A, is over 90% efficient, and supports a soft start function.Use the 4-wire serial port interface (SPI) for up to 40 MHz or the 2-wire I2C interface for up 1 MHz to configure each functional block and to collect the ADC data.APPLICATIONS Optical networking?100G/200G/400G or higher speed optical modulesFor more information on the AD1030, contact InfoOpticalNetwork@analog.com.

Demonstration circuit 2350B features the LTC6813-1, 18-channel battery-stack monitor. Multiple boards can be linked through a 2-wire isolated serial interface (isoSPI™) to monitor a long series of cells in a stack. The DC2350B demo board also features reversible isoSPI enabling a redundant communication path. The PCB, components, and DuraClik connectors are optimized for low EMI susceptibility and emissions. The DC2350B can communicate to a PC by connecting a DC2792B dual master isoSPI together with DC2026C Linduino® One. The DC2026 must be loaded with the appropriate program (called a sketch) to control the battery-stack monitor IC and receive data through a USB serial port. The DC2026 provides a standard SPI interface which can be translated to isoSPI and then connected to a DC2350B isoSPI port (J4 or J5 connector). The DC2792B companion board provides two SPI-isoSPI channels for reversible operation.

The AD9714/AD9715/AD9716/AD9717 are pin-compatible, dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC? converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and dc performance and support update rates up to 125 MSPS.The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9714/AD9715/AD9716/AD9717 make them well-suited for portable and low power applications.PRODUCT HIGHLIGHTS Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 35 mW at 125 MSPS with a 1.8 V supply. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows easy interfacing to other components that accept common- mode levels greater than 0 V.?APPLICATIONS Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The ADA4807-1 (single), ADA4807-2 (dual), and ADA4807-4 (quad) are low noise, rail-to-rail input and output, voltage feedback amplifiers. These amplifiers combine low power, low noise, high speed, and dc precision to provide an attractive solution for a wide range of applications from high resolution data acquisition instrumentation to high performance battery-powered and high component density systems where power consumption is of key importance.With only 1.0 mA of supply current per amplifier, the ADA4807-1/ADA4807-2/ADA4807-4 feature the lowest input voltage noise?among high speed, rail-to-rail input/output amplifiers in the industry and offer a wide bandwidth, high slew rate, fast settling time, and excellent distortion performance. Additionally, these amplifiers offer very low input offset voltage and drift performance, making them ideal for driving multiplexed and high throughput?precision 16-/18-bit successive approximation registers (SARs) and 24-bit ?-? ADCs.These amplifiers are fully specified at +3 V, +5 V, and ?5 V supplies and can operate over the industrial ?40?C to +125?C?temperature range.The ADA4807-1 is available in 6-lead SOT-23 and space-saving 6-lead SC70 packages. The ADA4807-2 is available in an 8-lead?MSOP and a compact, 3 mm ? 3 mm, 10-lead LFCSP. The ADA4807-4 is available in a 14-lead TSSOP package.Applications High resolution analog-to-digital converter (ADC) drivers Portable and battery-powered instruments and systems? High component density data acquisition systems Audio signal conditioning Active filters

The AD9520-2 provides a multioutput clock distributionfunction with subpicosecond jitter performance, along with anon-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHzto 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHzcan also be used.The AD9520-2 serial interface supports both SPI and I2C?ports.An in-package EEPROM, which can be programmed through theserial interface, can store user-defined register settings forpower-up and chip reset.The AD9520-2 features 12 LVPECL outputs in four groups. Anyof the 1.6 GHz LVPECL outputs can be reconfigured as two250 MHz CMOS outputs. If an application requires LVDSdrivers instead of LVPECL drivers, refer to the AD9522-2.Each group of three outputs has a divider that allows both thedivide ratio (from 1 to 32) and the phase offset or coarse timedelay to be set.The AD9520-2 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. The external VCO can have anoperating voltage of up to 5.5 V. A separate output driver powersupply can be from 2.375 V to 3.465 V.The AD9520-2 is specified for operation over the standardindustrial range of ?40?C to +85?C.Applications Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures

Together with an external loop filter and a voltage controlled crystal oscillator (VCXO), the HMC1031 forms a complete clock generator solution targeted at low frequency jitter attenuation and reference clock generation applications.The HMC1031 features a low power integer N divider, support-ing divide ratios of 1, 5, and 10, which is controlled via external hardware pins and requires no serial port.The integrated phase detector and charge pump are capable of operating at up to 140 MHz, and a maximum VCXO input of 500 MHz ensures frequency compliance with a wide variety of system clocks and VCXOs.Additional features include an integrated lock detect indicator available on a dedicated hardware pin, and a built in power-down mode.The HMC1031 is housed in an 8-lead MSOP package.APPLICATIONS Low jitter clock generation Low bandwidth (BW) jitter attenuation Low frequency phase-locked loops PLL Frequency translation Oven controlled crystal oscillator (OCXO) frequency multiplier Phase lock clean high frequency references to 10 MHz equipment