The?ADP1047?/ ADP1048 are digital power factor correction (PFC) controllers that provide accurate input power metering capability and inrush current control for ac/dc systems. The ADP1047 is designed for single phase PFC applications; the ADP1048 is designed especially for interleaved and bridgeless PFC applications.The digital PFC function is based on a conventional boost PFC with multiplication of the output voltage feedback combined with the input current and voltage to provide optimum harmonic correction and power factor for ac/dc systems. All signals are converted into the digital domain to provide maximum flexibility; all key parameters can be reported and adjusted via the PMBus? interface. The ADP1047 / ADP1048 allow users to optimize system performance, maximize efficiency across the load range, and reduce design time to market.The ADP1047 / ADP1048 provide accurate rms measurement of input voltage, current, and power. This information can be reported to the microcontroller of the power supply via thePMBus interface.APPLICATIONS AC/DC power supplies for applications Computing Server & Storage Network and communication infrastructure Industrial and Medical

The LTC3202 is a low noise, constant frequency charge pump DC/DC converter that uses fractional conversion to increase efficiency in white LED applications. The part can be used to produce a regulated voltage or current of up to 125mA from a 2.7V to 4.5V input. Low external parts count (two flying capacitors and two small bypass capacitors at VIN and VOUT) make the LTC3202 ideally suited for small, battery-powered applications.An internal 2-bit DAC allows LED current to be adjusted for LED brightness control. The LTC3202 also has thermal shutdown protection and can survive a continuous short-circuit from VOUT to GND. Built-in soft-start circuitry prevents excessive inrush current during start-up. High switching frequency enables the use of small external capacitors. A low current shutdown feature disconnects the load from VIN and reduces quiescent current to less than 1?A.The LTC3202 is available in the 10-pin MSOP and 3mm x 3mm DFN packages.Applications White LED Backlighting Programmable Boost Current Source?

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The HMC601LP4(E) Logarithmic Detector/Controller converts RF signals at its input, to a proportional DC voltage at its output. The HMC601LP4(E) employ a successive compression topology which delivers extremely high dynamic range and conversion accuracy over a wide input frequency range. As the input power is increased, successive amplifiers move into saturation one by one creating an accurate approximation of the logarithm function.The output of a series of square law detectors is summed, converted into voltage domain and buffered to drive the LOGOUT output. For detection mode, the LOGOUT pin is shorted to the VSET input, and will provide a nominal logarithmic slope of 19mV/dB and an intercept of -100 dBm. The HMC601LP4(E) can also be used in the controller mode where an external voltage is applied to the VSET pin, to create an AGC or APC feedback loop. The HMC601LP4(E) provides a 15/34ns (rise/fall time) response time enabling RF burst detection to a pulse rate beyond 20 MHz.Applications Cellular/PCS/3G WiMAX, WiBro & Fixed Wireless Power Monitoring & Control Circuitry Receiver Signal Strength Indication (RSSI) Automatic Gain & Power Control Circuits

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADM7172 is a CMOS, low dropout linear regulator (LDO) that operates from 2.3 V to 6.5 V and provides up to 2 A of output current. This high output current LDO is ideal for regulation of high performance analog and mixed-signal circuits operating from 6 V down to 1.2 V rails. Using an advanced proprietary architecture, the device provides high power supply rejection and low noise, and achieves excellent line and load transient response with just a small 4.7 ?F ceramic output capacitor. Load transient response is typically 1.5 ?s for a 1 mA to 1.5 A load step.The ADM7172 is available in 17 fixed output voltage options. The following voltages are available from stock: 1.3 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V, 4.2 V, and 5.0 V. Additional voltages that are available by special order are: 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.7 V, 2.75 V, 2.8 V, 2.85 V, 3.8 V, and 4.6 V. An adjustable version is also available that allows output voltages that range from 1.2 V to VIN ? VDO with an external feedback divider.Inrush current can be controlled by adjusting the start-up time via the soft start pin. The typical start-up time with a 1 nF soft start capacitor is 1.0 ms.The ADM7172 regulator output noise is 5 ?V rms, independent of the output voltage. The ADM7172 is available in an 8-lead, 3 mm ? 3 mm LFCSP, making it not only a very compact solution, but also providing excellent thermal performance for applications requiring up to 2 A of output current in a small, low profile footprint.Applications Regulation to noise sensitive applications: ADC and DAC circuits, precision amplifiers, PLLs/VCOs, and clocking ICs Communications and infrastructure Medical and healthcare Industrial and instrumentation

Demonstration circuit 1707 is a high efficiency monolithic step-down DC/DC switching regulator designed for double-data-rate (DDR) memory termination in computer systems. The VTT output is capable of sourcing and sinking up to 6A with an output voltage equal to one-half the voltage applied to the VDDQIN terminal or one-half the input supply voltage, selected by a jumper. An additional low current output (VTTR) also equal to one-half the voltage on VDDQIN can source and sink up to 10mA. Input voltage range is from 2.25V to 5.5V with overvoltage protection for transients exceeding 6.5V.

DC623A: Demo Board for the LTC3801 Micropower Constant Frequency Step-Down DC/DC Controllers in ThinSOT.

The HMC646LP2(E) is an SPDT switch in a leadless DFN surface mount plastic package for use in transmit / receive and LNA protection applications which require very low distortion and high power handling of up to 40 watts with less than 10% duty cycle. This robust switch can control signals from 100 - 2100 MHz* and is ideal for TD-SCDMA / 3G repeaters, PMR, automotive telematics, and satellite subscriber terminal applications. The design provides exceptional P0.1 dB of +46 dBm and +74 dBm IIP3 on the Transmit (Tx) port. The failsafe topology provides a low loss path from Tx to RFC, when no DC power is available.APPLICATIONS LNA Protection & T/R Switching TD-SCDMA / 3G Infrastructure Satellite Subscriber Terminals Private Mobile Radio & Public Safety Handsets Automotive Telematics

The AD8319 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibel-scaled output. It employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in either measurement or controller modes. The AD8319 maintains accurate log conformance for signals of 1 MHz to 8 GHz and provides useful operation to 10 GHz. The input dynamic range is typically 40 dB (re: 50 ?) with error less than ?1 dB. The AD8319 has 8 ns/10 ns response time (fall time/rise time) that enables RF burst detection to a pulse rate of beyond 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V is required to power the device. Current consumption is typically 22 mA, and it decreases to 200 ?A when the device is disabled.?The AD8319 can be configured to provide a control voltage to a power amplifier or a measurement output from the VOUT pin. Because the output can be used for controller applications, special attention was paid to minimize wideband noise. In this mode, the setpoint control voltage is applied to the VSET pin.The feedback loop through an RF amplifier is closed via VOUT, the output of which regulates the amplifier?s output to a magnitude corresponding to VSET. The AD8319 provides 0 V to (VPOS ? 0.1 V) output capability at the VOUT pin, suitable for controller applications. As a measurement device, VOUT is externally connected to VSET to produce an output voltage, VOUT, that is a decreasing linear-in-dB function of the RF input signal amplitude.The logarithmic slope is ?22 mV/dB, determined by the VSET interface. The intercept is 15 dBm (re: 50 ?, CW input) using the INHI input. These parameters are very stable against supply and temperature variations.The AD8319 is fabricated on a SiGe bipolar IC process and is available in a 2 mm ? 3 mm, 8-lead LFCSP_VD for an operating temperature range of ?40?C to +85?C.ApplicationsRF transmitter PA setpoint controls and level monitoring Power monitoring in radiolink transmitters RSSI measurement in base stations, WLANs, WiMAX, and radars