Demonstration circuit 806A features the LTC1867 Octal 16-bit ADC. The LTC1867 can be software programmed for a unipolar 0V to 4.096V or bipolar ±2.048V input range. The 8 channel multiplexer can be programmed for 8 single-ended inputs with respect to ground, 7 single-ended inputs with respect to the COM/CH7 pin, 4 differential inputs, or any combination of these.

Demonstration circuit 2071A features the LTC2373 family. The LTC2374/LTC2373/LTC2372 are low noise, high speed, 8-channel, 16/18-bit successive approximation register (SAR) ADCs. The demo manual refers to the LTC2373-18 but applies to all parts in the family, the only differences being the number of bits and the maximum sample rate. Operating from a single 5V supply, the LTC2373-18 has a highly configurable, low crosstalk, 8-channel input multiplexer, supporting fully differential, pseudo-differential unipolar and pseudo-differential bipolar analog input ranges.

The AD9114/AD9115/AD9116/AD9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC? converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and dc performance and support update rates up to 125 MSPS.The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/AD9115/AD9116/AD9117 make them well suited for portable and low power applications.PRODUCT HIGHLIGHTS Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 225 mW at 100 MSPS. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept common-mode levels greater than 0 V.?APPLICATIONS Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The ADAR4002 is a very low power broadband bi-directional single channel true time delay unit (TDU) and a digital step attenuator (DSA). The IC has 18.5 GHz of bandwidth over a frequency range of 0.5 GHz to 19 GHz with 50 ? input impedance at both RF ports. The TDU has two programmable maximum time delays, each with 7-bit control: Range 0 has a maximum delay of 508ps with a resolution of 4ps. This range is used at lower frequencies and where the ADAR4002 has less loss. Range 1 has a maximum delay of 254ps and a resolution of 2ps. This range has less loss compared to Range 0 and is useful at higher frequencies. The DSA has 6-bit resolution with an attenuation range of 0 dB to 31.5 dB and a step size of 0.5 dB. The ADAR4002 is designed to provide flexible digital control through either a SPI interface or a shift register to allow daisy chaining multiple chips together. The ADAR4002 contains register memory for 32 TDU+DSA states. The memory combined with on-chip sequencers, allows a fast memory advance via the UPDATE pin.The ADAR4002 is available in a 2 mm ? 3 mm 14-lead LFCSP package and is specified from -40?C to 85?C.APPLICATIONSElectronic steerable antenna arraysMulti-Function ArraysSATCOMRADARData LinksTest Equipment

The ADRV9008-2 is a highly integrated, RF agile transmit subsystem offering dual channel transmitters, observation path receiver, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 2G, 3G and 4G macro-cell base stations, and active antenna, applications.The transmitters use an innovative direct conversion modulator that achieves multi-carrier macro-base-station quality performance and very low power. In 3G/4G mode, the maximum large-signal bandwidth is 200MHz. In MC-GSM mode, which has higher in-band SFDR, the maximum large-signal bandwidth is 75MHz.The observation path consists of a wide bandwidth direct-conversion receiver with state-of-the-art dynamic range. The complete receive subsystem includes dc offset correction, quadrature correction, and digital filtering thus eliminating the need for these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-front-end control are also integrated. The fully integrated phase locked loops (PLLs) provide high performance, low power fractional-N RF frequency synthesis for the transmitter and receiver sections. An additional synthesizer is used to generate the clocks needed for the converters, digital circuits, and the serial interface. Special precautions have been taken to provide the isolation demanded in high performance base station applications. All VCO and loop filter components are integrated.The high-speed JESD204B interface supports up to 12.288 Gbps lane rates resulting in two lanes per transmitter in the widest bandwidth mode and two lanes for the observation path receiver in the widest bandwidth mode. The core of the ADRV9008-2 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4 wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9008-2 is packaged in a 12mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

The EVAL-ADXL367Z is a simple breakout board that enables easy connection of an ADXL367 into an existing system. The ADXL367 is a nanowatt, 3-axis, digital-output accelerometer whose industry leading low power consumption and built-in features make it ideal for use in a wide variety of applications. Due to its small size, the EVAL-ADXL367Z has minimal effect on performance of the system and of the accelerometer, and thus it is ideal for evaluation of the ADXL367 in an existing system. Note that the ADXL367 must be communicated with digitally via SPI or I2C. No processor is included with the EVAL-ADXL367Z; firmware must be supplied externally by the user. For evaluation boards that include a processor, please see the EVAL-ADXL367-SDP. MARKETS & TECHNOLOGY Industrial Digital Healthcare Prosumer Automotive Aerospace and Defense

The ADCMP606 and ADCMP607 are very fast comparatorsfabricated on XFCB2, an Analog Devices, Inc., proprietaryprocess. These comparators are exceptionally versatile and easyto use. Features include an input range from VEE ? 0.5 V toVCCI + 0.2 V, low noise, CML-compatible output drivers, andTTL-/CMOS-compatible latch inputs with adjustable hysteresisand/or shutdown inputs.The devices offer 1.25 ns propagation delay with 2.5 ps rmsrandom jitter (RJ). Overdrive and slew rate dispersion aretypically less than 50 ps.A flexible power supply scheme allows the devices to operatewith a single +2.5 V positive supply and a ?0.5 V to +2.7 Vinput signal range up to a +5.5 V positive supply with a ?0.5 Vto +5.7 V input signal range. The ADCMP607 features splitinput/output supplies with no sequencing restrictions tosupport a wide input signal range with independent outputswing control and power savings.The CML-compatible output stage is fully back-matched forsuperior performance. The comparator input stage offers robustprotection against large input overdrive, and the outputs do notphase reverse when the valid input signal range is exceeded. Onthe ADCMP607, latch and programmable hysteresis features arealso provided with a unique single-pin control option.The ADCMP606 is available in a 6-lead SC70 package and theADCMP607 is available in a 12-lead LFCSP package.Applications High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE)

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The LTC6948 is a high performance, low noise, 6.39GHz phase-locked loop (PLL) with a fully integrated VCO, including a reference divider, phase-frequency detector (PFD), ultralow noise charge pump, fractional feedback divider, and VCO output divider.The fractional divider uses an advanced, 4th order ?? modulator which provides exceptionally low spurious levels. This allows wide loop bandwidths, producing extremely low integrated phase noise values.The programmable VCO output divider, with a range of 1 through 6, extends the output frequency range.Applications Wireless Basestations (LTE, WiMAX, W-CDMA, PCS) Microwave Data Links Military and Secure Radio Test and Measurement

The LTC2325-14 is a low noise, high speed quad 14-bit + sign successive approximation register (SAR) ADC with differential inputs and wide input common mode range. Operating from a single 3.3V or 5V supply, the LTC2325-14 has an 8VP-P differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. The LTC2325-14 achieves ?1LSB INL typical, no missing codes at 14 bits and 81dB SNR.The LTC2325-14 has an onboard low drift (20ppm/?C max) 2.048V or 4.096V temperature-compensated reference. The LTC2325-14 also has a high speed SPI-compatible serial interface that supports CMOS or LVDS. The fast 5Msps per channel throughput with one cycle latency makes the LTC2325-14 ideally suited for a wide variety of high speed applications. The LTC2325-14 dissipates only 45mW per channel and offers nap and sleep modes to reduce the power consumption to 26?W for further power savings during inactive periods.Applications High Speed Data Acquisition Systems Communications Optical Networking Multiphase Motor Control