The ADP2300 / ADP2301?are compact, constant-frequency, current-mode, step-down dc-to-dc regulators with integrated power MOSFET. The ADP2300 / ADP2301 devices run from any input voltage from 3.0 V up to 20 V, making them suitable for a wide range of applications. A precise, low voltage internal reference makes these devices ideal for generating a regulated output voltage as low as 0.8 V, with ?2% accuracy, for up to 1.2 A load current.There are two frequency options: the ADP2300 runs at 700 kHz and the ADP2301 runs at 1.4 MHz. These options allow users to make decisions based on the trade-off between efficiency and the size of the total solution. Current-mode control provides fast and stable line and load transient performance. Each ADP2300 / ADP2301 device includes an internal soft start to prevent inrush current at power up. Other key safety features include short-circuit protection, thermal shutdown (TSD) and input undervoltage lockout (UVLO). Precision enable pin threshold voltage allows ADP2300 / ADP2301 to be easily sequenced from other input/output supplies, or the enable pin can be used as a programmable UVLO input by using resistive divider.The ADP2300 / ADP2301 are available in a 6-lead TSOT package and are rated for the ?40?C to +125?C junction temperature range.APPLICATIONS LDO replacement for digital load applications Intermediate power rail conversion Communications and networking Industrial and instrumentation Healthcare and Medical Consumer

The AD7766/AD7766-1/AD7766-2 are high performance,24-bit, oversampled SAR analog-to-digital converters (ADCs).The AD7766/AD7766-1/AD7766-2 combine the benefits of alarge dynamic range and input bandwidth, consuming 15 mW,10.5 mW, and 8.5 mW power, respectively, and are contained ina 16-lead TSSOP package.Ideal for ultralow power data acquisition (such as PCI- and USBbasedsystems), the AD7766/AD7766-1/AD7766-2 provide 24-bitresolution. The combination of exceptional SNR, wide dynamicrange, and outstanding dc accuracy make the AD7766/AD7766-1/AD7766-2 ideally suited for measuring small signal changes over awide dynamic range. This is particularly suitable for applicationswhere small changes on the input are measured on larger ac ordc signals. In such an application, the AD7766/AD7766-1/AD7766-2 accurately gather both ac and dc information.The AD7766/AD7766-1/AD7766-2 include an on-board digitalfilter (complete with linear phase response) that acts to eliminateout-of-band noise by filtering the oversampled input voltage.The oversampled architecture also reduces front-end antialiasrequirements. Other features of the AD7766/AD7766-1/AD7766-2include a SYNC/PD (synchronization/power-down) pin, allowingthe synchronization of multiple AD7766/AD7766-1/AD7766-2devices. The addition of an SDI pin provides the option of daisychaining multiple AD7766/AD7766-1/AD7766-2 devices.The AD7766/AD7766-1/AD7766-2 operate from a 2.5 V supplyusing a 5 V reference. The devices operate from ?40?C to +105?C. Applications Low power PCI/USB data acquisition systems Low power wireless acquisition systems Vibration analysis Instrumentation High precision medical acquisition

The SSM2380 is a fully integrated, high efficiency, stereo, Class-D audio amplifier. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a single 2.5 V to 5.5 V supply. It is capable of delivering 2 W of continuous output power with 100 dB.Spread-spectrum pulse density modulation is used to provide lower EMI-radiated emissions compared with other Class-D architectures. An added benefit of spread-spectrum ?-? modu-lation is that no synchronization (SYNC) is needed when using multiple Class-D amplifiers. For applications that require long speaker cables (>10 cm), the SSM2380 includes a user-selectable ultralow EMI emissions mode that eliminates the need for EMI filters at the Class-D outputs.The SSM2380 has a micropower shutdown mode with a typicalshutdown current of 20 nA. Shutdown is enabled by applying alogic low to the SD pin or through an optional independent channel soft shutdown via I2C.The device also includes pop-and-click suppression circuitry. Thissuppression circuitry minimizes voltage glitches at the outputduring turn-on and turn-off, reducing audible noise on activationand deactivation.The fully differential inputs of the SSM2380 provides excellentrejection of common-mode noise on the input. Input couplingcapacitors can be omitted if the dc input common-mode voltage isapproximately VDD/2.The SSM2380 is specified over the commercial temperature range(?40?C to +85?C). It has built-in thermal shutdown and outputshort-circuit protection. It is available in a 16-ball, 2 mm ? 2 mmwafer level chip scale package (WLCSP).Applications Mobile phones MP3 players Portable electronics

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9217 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9217 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER).The AD9217 features a low latency, high speed, parallel CML output interface that supports full bandwidth operation with compatible FPGA/ASIC receivers. The AD9217 can be reconfigured to operate in native AD9213 mode for applications requiring additional digital processing and JESD204B output support. Refer to the AD9213 data sheet?when operating the AD9217 in AD9213 mode.The AD9217 achieves dynamic range and linearity performance while consuming 4.2 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9217 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.The AD9217 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is specified over the industrial temperature range of -40?C to +85?C.PRODUCT HIGHLIGHTS Small Footprint. Eight ADCs are contained in a small, space-saving package. Low power of 114 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9212 (10-bit) and AD9252 (14-bit).APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment

The AD9230 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9230 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 64.9 dBFS SNR @ 250 MSPS with a 70 MHz input. Low Power?Consumes only 434 mW @ 250 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample and hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?10-bit pin-compatible family offered as AD9211.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9230 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9230 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 64.9 dBFS SNR @ 250 MSPS with a 70 MHz input. Low Power?Consumes only 434 mW @ 250 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample and hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?10-bit pin-compatible family offered as AD9211.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB? and SYSREF?) are provided.Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported for each channel via the dedicated fast detect pins.Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.Product Highlights Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC. The configurable JESD204B output block supports up to 5 Gbps per lane. An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. Support for an optional RF clock input to ease system board design. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.Applications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers I/Q demodulation systems Smart antenna systems Electronic test and measurement equipment Radar receivers COMSEC radio architectures IED detection/jamming systems General-purpose software radios Broadband data applications