The AD9608 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC) that features a high performance sample-and-hold circuit and an on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Logic levels of 1.8 V CMOS and 1.8 V LVDS are supported. Output data can also be multiplexed onto a single output bus.The AD9608 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS Operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or 1.8 V LVDS logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. Includes a standard serial port interface that supports various product features and functions, such as data output format-ting, internal clock divider, power-down, DCO/data timing, and offset adjustments. Packaged in a 64-lead, RoHS-compliant LFCSP that is pin compatible with the AD9650, AD9269 and AD9268 16-bit ADC?s, the AD9258 and AD9648 14-bit ADC, the AD9628 and AD9231 12-bit ADC?s, and the AD9204 10-bit ADC?s, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.APPLICATIONS Communications Diversity radio systems I/Q demodulation systems Broadband data applications Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound

The AD9626 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are CMOS compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9626 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 64.9 dBFS SNR @ 250 MSPS with a 70 MHz input. Low Power?Consumes only 364 mW @ 250 MSPS. Ease of Use?CMOS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?10-bit pin-compatible family offered as the AD9601.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9633 is available in a RoHS-compliant, 48-lead LFCSP. It is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent. Applications Medical ultrasound High speed imaging Quadrature radio receivers Diversity radio receivers Test equipment

The AD9644 is a dual, 14-bit, analog-to-digital converter (ADC) with a high speed serial output interface and sampling speeds of either 80 MSPS or 155 MSPS.The AD9644 is designed to support communications appli-cations where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.By default, the ADC output data is routed directly to the two external JESD204A serial output ports. These outputs are at CML voltage levels. Two modes are supported such that output coded data is either sent through one data link or two. (L = 1; F = 4 or L = 2; F = 2). Independent synchronization inputs (DSYNC) are provided for each channel.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9644 is available in a 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.This product is protected by a U.S. patent.Applications Communications Diversity radio systems Multimode digital receivers (3G and 4G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipmentProduct Highlights An on-chip PLL allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding data rate clock. The configurable JESD204A output block supports up to 1.6 Gbps per channel data rate when using a dedicated data link per ADC or 3.2 Gbps data rate when using a single shared data link for both ADCs. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.

The AD9683 is a 14-bit ADC with sampling speeds of up to250 MSPS. The AD9683 supports communications applicationswhere low cost, small size, wide bandwidth, and versatility aredesired.The ADC core features a multistage, differential pipelinedarchitecture with integrated output error correction logic. TheADC core features wide bandwidth inputs supporting a varietyof user-selectable input ranges. An integrated voltage referenceeases design considerations. A duty cycle stabilizer (DCS) isprovided to compensate for variations in the ADC clock duty cycle,allowing the converter to maintain excellent performance. TheJESD204B high speed serial interface reduces board routingrequirements and lowers pin count requirements for thereceiving device.The ADC output data is routed directly to the JESD204B serialoutput lane. These outputs are at CML voltage levels. Data can besent through the lane at the maximum sampling rate of 250 MSPS,which results in a lane rate of 5 Gbps. Synchronization inputs(SYNCINB? and SYSREF?) are provided.Flexible power-down options allow significant power savings,when desired. Programmable overrange level detection issupported via the dedicated fast detect pins.Programming for setup and control is accomplished using a3-wire SPI-compatible serial interface.The AD9683 is available in a 32-lead LFCSP and is specifiedover the industrial temperature range of ?40?C to +85?C.Product Highlights Integrated 14-bit, 170 MSPS/250 MSPS ADC. The configurable JESD204B output block supports lane rates up to 5 Gbps. An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. Support for an optional radio frequency (RF) clock input to ease system board design. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration.Applications Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Smart antenna systems Electronic test and measurement equipment Radar receivers COMSEC radio architectures IED detection/jamming systems General-purpose software radios Broadband data applications Ultrasound equipment

The AD9986 is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate RF DAC core, and a 12-bit, 6 GSPS rate RF ADC core. The AD9986 supports four transmitter channels and two receiver channels with four transmitter, two receiver (4T2R) configuration. The AD9986 is well suited for 2-antenna and 4-antenna transmitter applications requiring a wide bandwidth observation receiver path for the digital predistortion. The AD9986 supports up to a 6 GSPS complex transmit and receive data rate in single channel mode. The maximum radio channel bandwidth supported is 1.2 GHz and 2.4 GHz for the transmit and receive paths, respectively (4T2R). The AD9986 features a 16 lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B serial data port, an on-chip clock multiplier, and digital signal processing capability targeted at multiband, direct-to-RF radio applications. APPLICATIONS Wireless communications infrastructure W-CDMA, LTE, LTE-A, Massive-MIMO Microwave point-to-point, E-band, and 5G mm Wave Broadband communications systems DOCSIS 3.1 and 4.0 CMTS Communications test and measurement system

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs.The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device.The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection.This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of ?40?C to +85?C.APPLICATIONSLow jitter clock distributionClock and data signal restorationLevel translationWireless communicationsWired communicationsMedical and industrial imagingATE and high performance instrumentation

The ADL5243 is a high performance, digitally controlled variable gain amplifier operating from 100 MHz to 4000 MHz.The VGA integrates two high performance amplifiers and a digital step attenuator (DSA). Amplifier 1 (AMP1) is an internally matched gain block amplifier with 20 dB gain, and Amplifier 2 (AMP2) is a broadband ? W driver amplifier that requires very few external tuning components. The DSA is 6-bit with a 31.5 dB gain control range, 0.5 dB steps, and ?0.25 dB step accuracy. The attenuation of the DSA can be controlled using a serial or parallel interface.The gain block and DSA are internally matched to 50 ? at their inputs and outputs, and all three internal devices are separately biased. The separate bias allows all or part of the ADL5243 to be used, which allows for easy reuse throughout a design. The pinout of the ADL5243 also enables the gain block, DSA, or ? W driver amplifier to be first, giving the VGA maximum flexibility in a signal chain.The ADL5243 consumes 175 mA and operates off a single supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a thermally efficient, 5 mm ? 5 mm, 32-lead LFCSP and is fully specified for operation from ?40?C to +85?C. A fully populated evaluation board is available.ApplicationsWireless infrastructureAutomated test equipmentRF/IF gain control

The ADL5391 draws on three decades of experience in advanced analog multiplier products. It provides the same general mathematical function that has been field proven to provide an exceptional degree of versatility in function synthesis:VW?= ? ? (VX?x VY)/1 V + VZThe most significant advance in the ADL5391 is the use of anew multiplier core architecture, which differs markedly fromthe conventional form that has been in use since 1970. Theconventional structure that employs a current mode, translinearcore is fundamentally asymmetric with respect to the X and Yinputs, leading to relative amplitude and timing misalignmentsthat are problematic at high frequencies. The new multiplier coreeliminates these misalignments by offering symmetric signalpaths for both X and Y inputs. The Z input allows a signal to beadded directly to the output. This can be used to cancel a carrieror to apply a static offset voltage.The fully differential X, Y, and Z input interfaces are operationalover a ?2 V range, and they can be used in single-ended fashion.The user can apply a common mode at these inputs to varyfrom the internally set VPOS/2 down to ground. If these inputsare ac-coupled, their nominal voltage will be VPOS/2. These inputinterfaces each present a differential 500 ? input impedance up toapproximately 700 MHz, decreasing to 50 ? at 2 GHz. The gainscaling input, GADJ, can be used for fine adjustment of the gainscaling constant (?) about unity.The differential output can swing ?2 V about the VPOS/2common-mode and can be taken in a single-ended fashion aswell. The output common mode is designed to interface directlyto the inputs of another ADL5391. Light dc loads can be groundreferenced; however, ac-coupling of the outputs is recommendedfor heavy loads.The ENBL pin allows the ADL5391 to be disabled quickly to astandby mode. It operates off supply voltages from 4.5 V to 5.5 Vwhile consuming approximately 130 mA.The ADL5391 is fabricated on Analog Devices, Inc. proprietary,high performance, 65 GHz, SOI complementary, SiGe bipolarIC process. It is available in a 16-lead, RoHS compliant, LFCSPand operates over a ?40?C to +85?C temperature range.Evaluation boards are available.Applications Wideband multiplication and summing High frequency analog modulation Adaptive antennas (diversity/phased array) Square-law detectors and true rms detectors Accurate polynomial function synthesis DC capable VGA with very fast control

The ADL5506 is a complete, low cost subsystem for the measurement of RF signals in the 30 MHz to 4.5 GHz frequency range, with a typical dynamic range of 45 dB, intended for use in a wide variety of wireless terminal devices. It provides a wider dynamic range and better accuracy than is possible using discrete diode detectors. In particular, its temperature stability is excellent over ?40?C to +85?C.Its high sensitivity allows measurement of low power levels, thus reducing the amount of power that needs to be coupled to the detector. It is essentially a voltage responding device, with a typical dynamic range of 45 dB.For convenience, the signal is internally ac-coupled, using a 5 pF capacitor and a broadband 50 ? match, with an external shunt resistor of 52 ?. This high-pass coupling, with a corner at approximately 19 MHz, determines the lowest operating frequency. Therefore, the source can be dc grounded.The ADL5506 output increases from approximately 0.14 V to a little over 1 V as the input signal level increases from 1.25 mV rms (?45 dBm) to 224 mV rms (0 dBm). The output is proportional to the logarithm of the input power level; that is, the reading is presented directly in decibels and is scaled about 18 mV/dB at 900 MHz. A capacitor can be connected between the VLOG pin and the CFLT pin when it is desirable to increase the time interval over which averaging of the input waveform occurs.The ADL5506 is available in a 6-ball WLCSP and consumes 3.8 mA from a 3.0 V supply. When powered down, the typical disable supply current is <1 ?A.Applications RSSI and TSSI for wireless terminal devices RF transmitter or receiver power measurement Automotive RF bidirectional amplifiers