The ADN4654/ADN4655/ADN46561? are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain.The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation.Applications Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

The ADN4654/ADN4655/ADN46561? are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain.The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation.Applications Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

The ADPD105/ADPD106/ADPD107 are highly efficient,photometric front ends, each with an integrated 14-bit analog-to-digitalconverter (ADC) and a 20-bit burst accumulator thatworks with flexible light emitting diode (LED) drivers. Theaccumulator is designed to stimulate an LED and measurethe corresponding optical return signal. The data output andfunctional configuration occur over a 1.8 V I2C interface on theADPD105 or SPI on the ADPD106 and ADPD107. The controlcircuitry includes flexible LED signaling and synchronousdetection.The analog front end (AFE) features best-in-class rejection of signaloffset and corruption due to modulated interference commonlycaused by ambient light.Couple the ADPD105/ADPD106/ADPD107 with a lowcapacitance photodiode of <100 pF for optimal performance.The ADPD105/ADPD106/ADPD107 can be used with any LED.The ADPD105 is available in a 2.46 mm ? 1.4 mm WLCSP and a4 mm ? 4 mm LFCSP. The SPI only versions, ADPD106 andADPD107, are available in a 2.46 mm ? 1.4 mm WLCSP.Applications Wearable health and fitness monitors Clinical measurements, for example, SpO2 Industrial monitoring Background light measurements

The ADPD4200 operates as a complete multimodal sensor front end, stimulating up to four light emitting diodes (LEDs) and measuring the return signal on up to four separate current inputs. Twelve time slots are available, enabling 12 separate measurements per sampling period.The data output and functional configuration utilize a serial port interface (SPI) on the ADPD4200. The control circuitry includes flexible LED signaling and synchronous detection. The device uses a 1.8 V analog core and 1.8 V or 3.3 V compatible digital input/output (I/O).The analog front end (AFE) rejects signal offsets and corruption from asynchronous modulated interference, typically from ambient light, eliminating the need for optical filters or externally controlled dc cancellation circuitry. Multiple operating modes are provided, enabling the ADPD4200 to be a sensor hub for synchronous measurements of photodiodes, biopotential electrodes, resistance, capacitance, and temperature sensors.The ADPD4200 is available in a 2.619 mm ? 1.804 mm, 0.40 mm pitch, 24-ball WLCSP.Analog Devices is in the process of updating documentation to provide terminology and language that is culturally appropriate. This is a process with a wide scope and will be phased in as quickly as possible. Thank you for your patience.APPLICATIONS Wearable health and fitness monitors: heart rate monitors (HRMs), heart rate variability (HRV), stress, blood pressure estimation, SpO2, hydration, and body composition Industrial monitoring: CO, CO2, smoke, and aerosol detection Home patient monitoring

The ADPD6000 is a highly integrated analog front end (AFE) designed for measuring various vital signals.The optical channel is designed as an optical transceiver, stimulating up to four light emitting diodes (LEDs) and measuring the return signal on up to four separate current inputs. The signal chain rejects signal offsets and corruption from asynchronous modulated interference, typically from ambient light, eliminating the need for optical filters or externally controlled dc cancellation circuitry.The electrocardiography (ECG) signal acquisition is designed to support low noise, diagnostic level measurement in the presence of a variety of interferers. The ECG signal chain has a number of complementary features supporting ECG measurement, such as driven reference for common-mode rejection and lead off detection to identify a fallen electrode.The body impedance analysis (BIA) signal chain is designed for body impedance measurement with a configurable excitation path and measurement path. A 12-bit digital-to-analog (DAC) is used in the excitation path to generate the sinusoid wave and high precision measurement, with configurable filters used to measure the body response of the stimulus.The data output and functional configuration use a serial port interface (SPI) on the ADPD6000. The control circuitry includes flexible LED signaling and synchronous detection, digital filters, digital wave generators, and configurable filters.The ADPD6000 is available in a 2.6 mm ? 2.6 mm, 0.4 mm pitch, 36-ball wafer level chip scale package (WLCSP).APPLICATIONS Wearable health and fitness monitors: heart rate, heart rate variability, SpO2, body impedance analysis, hydration, cuffless noninvasive blood pressure Home patient monitoring Industrial monitoring: particle and aerosol, gas, and conductivity detection

DC996B-J - Demo Board for the LTC2215 16-Bit, 65Msps Low Noise ADC.

DC997B-A - Demo Board for the LTC2242-12 12-Bit, 250Msps ADC.

The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. The HMC7044 features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs).The DCLK and SYSREF clock outputs of the HMC7044 can be configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses.APPLICATIONS JESD204B clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Microwave baseband cards Phase array reference distribution

The HMC8100LP6JE is a highly integrated IF receiver chip that converts radio frequency (RF) input signals ranging from 800 MHz to 4000 MHz down to a single ended intermediate frequency (IF) signal of 140 MHz at its output. The IF receiver chip is housed in a compact 6 mm x 6 mm LFCSP package and supports complex modulations up to 1024 QAM. The HMC8100LP6JE device includes two VGAs, three power detectors, a programmable AGC block, and selected integrated bandpass filters with 14 MHz, 28 MHz, 56 MHz, and 112 MHz bandwidth. The HMC8100LP6JE also supports baseband IQ interfaces after the mixer so that the chips can be used in the full ODU configuration.The HMC8100LP6JE supports all of the standard microwave frequency bands from 6 to 42 GHz.Applications Point to point communications Satellite communications Wireless microwave backhaul systemsPlease also view complimentary product HMC8200, Intermediate Frequency Transmitter 800 MHz - 4000 MHz.

The HMC1035LP6GE is a low-noise, wide-band 3.3 V clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 25 MHz and 2500 MHz range. The HMC1035LP6GE features a low noise Phase Detector (PD) and Delta-Sigma modulator, capable of operating at up to 100 MHz which permits wider loop-bandwidths and excellent spurious performance.The HMC1035LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (<-162 dBc/Hz) makes the HMC1035LP6GE an ideal source for a variety of applications?such as clock references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SER DES) circuits, FPGAs and processors. The HMC1035LP6GE can also be used as an LO for 10G/40G/100G optical modules and transponders, as well as primary reference clock for 10G/40G/100G line cards, and for jitter attenuation and frequency translation.The differential output of the HMC1035LP6GE can be set to either External Termination, which could be used for LVPECL operation, or Internal Termination for operation in an LVDS compatible mode or LVPECL. Additionally, an ouput swing adjustment makes the device flexible and compatible with a wide variety of signal level requirements. The output can be internally terminated to reduce component count and cost or could be terminated externally using standard LVPECL termination methods. An Output Mute function allows the user to shut off the outputs, such as may be required for board testing or debugging. The LVPECL/LVDS, amplitude select and Output Mute function are all programmed SPI serial programming.The HMC1035LP6GE is designed to select between a Power Priority or a Performance Priority mode. The Power Priority setting reduces the current consumption of the part, whereas the Performance Priority setting improves the Jitter and Phase Noise performance.The 24 bit Delta-Sigma Modulator further enhances Hittite?s Exact Frequency Mode, which enables users to generate output frequencies with 0 Hz frequency error in many applications.APPLICATIONS 10G/40G/100G Optical Modules, Transponders, Line Cards OTN and SONET /SDH Applications Data Converters, Sample Clock Generation Cellular/4G Infrastructure High Frequency Processor/FPGA Clocks Any Frequency Clock Rate Generation Low Jitter SAW Oscillator Replacement DDS Replacement Frequency Translation Frequency Margining