16-Channel, 12-/16-Bit nanoDAC+ with 2 ppm/C Voltage Reference TC, I2C Interface Features: High relative accuracy (INL): ±4 LSB maximum at 16 bits (AD5677R only) TUE: ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Low drift, 2.5 V voltage reference TC: 2 ppm/°C typical 40 mA short-circuit current Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply range Simplified implementation User selectable gain of 1 or 2 (GAIN pin) 1.8 V logic compatibility 400 kHz I2C-compatible serial interface 28-lead, 4 mm × 4 mm, RoHS compliant LFCSP

Single-Channel, 16-Bit Current and Voltage Output DAC with Dynamic Power Control and HART Connectivity Features: 16-bit resolution and monotonicity DPC for thermal management Current/voltage output available on a single terminal Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, 0 mA to 24 mA, ±20 mA, ±24 mA, −1 mA to +22 mA Voltage output ranges (with 20% overrange): 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V User-programmable offset and gain Advanced on-chip diagnostics, including a 12-bit ADC On-chip reference Robust architecture, including output fault protection EMC test standards: IEC 61000-4-6 conducted immunity (10 V, Class A) IEC 61000-4-3 radiated immunity (20 V/m, Class A) IEC 61000-4-2 ESD (±6 kV contact, Class B) IEC 61000-4-4 electrical fast transient (EFT) (±4 kV, Class B) IEC 61000-4-5 surge (±4 kV, Class B) 32-lead, 5 mm × 5 mm LFCSP −40°C to +115°C temperature range

+2.5V to 5.5V, 230 A Dual Rail-to-Rail Voltage Output 12-Bit DAC with Parallel Interface in 28-lead TSSOP Features: Dual 12-Bit DAC in 28-Lead TSSOP Low Power: 300 µA @ 5 V, 230 µA @ 3 V Power-Down to 200 nA @ 5 V, 80 nA @ 3 V Guaranteed Monotonic by Design Power-On-Reset to Zero Volts Double-Buffered Input Logic Simultaneous Update of DAC Outputs via LDAC pin (active low) Asynchronous Clear Facility via CLR pin (active low) Low Power Parallel Data Interface Temperature Range: -40°C to 105°C

8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification) Crosspoint multiplexed analog inputs 8 differential/15 pseudo differential inputs See data sheet for additional features

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC Features: Recommended pin to pin extended temperature range upgrade AD4134 Alias free: inherent antialias rejection of 102.5 dB typical in high performance mode Excellent ac and dc performance 108 dB dynamic range at ODR = 374 kSPS, FIR filter, typical 137 dB dynamic range at ODR = 10 SPS, sinc3 filter, typical THD: −120 dB typical with 1 kHz input tone Offset error drift: 0.7 µV/°C typical Gain drift: 2 ppm/°C typical INL: ±2 ppm of FSR typical Dynamic range enhancement: 4:1 and 2:1 averaging mode 126 dB, A weighted dynamic range Resistive ADC and reference input Easy to sync: asynchronous sample rate converter Multidevice synchronization with one signal line Programmable data rates from 0.01 kSPS to 1496 kSPS with resolution of 0.01 SPS Option to control output data rate by external signal Linear phase digital filter options Low ripple FIR filter: 32 µdB pass-band ripple, dc to 161.942 kHz Low latency sinc3 filter and sinc6 filter, dc to 391.5 kHz Sinc3 filter with 50 Hz/60 Hz rejection Crosstalk: 130.7 dBFS Daisy-chaining CRC error checking on data and SPI interface Two power modes: high performance mode and low power mode Power supply: 4.5 V to 5.5 V and 1.65 V to 1.95V 1.8 V IOVDD level External reference: 4.096 V or 5V Crystal or external CMOS clock of 48 MHz SPI or pin (standalone) configurable operation Operating temperature range: 0°C to 85°C Available in 8 mm × 8 mm, 56-lead LFCSP with exposed pad

16-Bit 8/10-Channel, Low Voltage, Low Power, Sigma Delta ADC Features: 8-/10-Channel, High Resolution Σ-Δ ADCs 16-Bit Resolution Factory-Calibrated Single Conversion Cycle Setting Programmable Gain Front End Simultaneous 50 Hz and 60 Hz Rejection VREF Select™ Allows Absolute and Ratiometric Measurement Capability Operation Can Be Optimized for Analog Performance (CHOP = 0) or Channel Throughput (CHOP= 1)

CMOS, 24-Bit Signal Conditioning ADC with Current Source Features: Charge Balancing ADC 24 Bits, No Missing Codes ±0.0015% Nonlinearity 2-Channel Programmable Gain Front End Gains from 1 to 128 Differential Inputs Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write Calibration Coefficients Bidirectional Microcontroller Serial Interface Internal/External Reference Option Single- or Dual-Supply Operation Low Power (25 mW Typ) with Power-Down Mode (7 mW Typ)

24-Bit, 8/10-Channel, Low Voltage, Low Power, Sigma Delta ADC Features:8-/10-Channel, High Resolution - ADCs 24-Bit Resolution Factory-Calibrated Single Conversion Cycle Setting Programmable Gain Front End Simultaneous 50 Hz and 60 Hz Rejection VREF Select Allows Absolute and Ratiometric Measurement Capability Operation Can Be Optimized for- Analog Performance (CHOP = 0) or - Channel Throughput (CHOP = 1)

20-Bit, Pin-Programmable, Ultralow Power Sigma-Delta ADC Features:Pin-programmable filter responseUpdate rate: 10 Hz or 16.7 HzPin-programmable in-amp gainPin-programmable power-down and resetStatus functionInternal clock oscillatorInternal bridge power-down switchCurrent:115 A typical (Gain = 1)330 A typical (Gain = 128)Simultaneous 50 Hz/60 Hz rejectionPlease see data sheet for additional features