Low Power 400MHz Blackfin+ Embedded Processor with 256KByte L2 SRAM Features: Blackfin+ core with up to 400 MHz performance Dual 16-bit or single 32-bit MAC support per cycle 16-bit complex MAC and many other instruction set enhancements Instruction set compatible with previous Blackfin product On-Chip Memory 136KB L1 SRAM with multi-parity-bit protection (64KB instruction, 64KB data, 8KB scratchpad) 256KByte on-chip L2 SRAM with ECC protection 512KByte On-chip L2 ROM Key Peripherals include USB2.0 HS OTG 2x CAN2.0B ePPI Video I/O 2x SPORTs (w/I2S) 2xQuad-SPI / 1xDual-SPI (w/ Host mode option) I2C 2xUART SD/SDIO/MMC (4-bit) Security and one-time-programmable memory Crypto hardware accelerators for fast secure boot/IP protection memDMA encryption/decryption for fast run-time security Low-cost packaging 88-Lead LFCSP (QFN) package (12 mm × 12mm), RoHS compliant Low system power with < 100 mW at 400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION

Low Power 400MHz Blackfin+ Embedded Processor with 256KByte L2 SRAM & DDR2/LPDDR Interface Features: Blackfin+ core with up to 400 MHz performance Dual 16-bit or single 32-bit MAC support per cycle 16-bit complex MAC and many other instruction set enhancements Instruction set compatible with previous Blackfin product On-Chip Memory 136KB L1 SRAM with multi-parity-bit protection (64KB instruction, 64KB data, 8KB scratchpad) 256KByte on-chip L2 SRAM with ECC protection 512KByte On-chip L2 ROM L3 interface providing 16-bit interface to DDR2 or LPDDR SDRAM devices (up to 200 MHz) Key Peripherals include USB2.0 HS OTG 2x CAN2.0B ePPI Video I/O 2x SPORTs (w/I2S) 2xQuad-SPI / 1xDual-SPI (w/ Host mode option) I2C 2xUART SD/SDIO/MMC (8-bit) 4-ch 12-bit 1MSPS ADC Security and one-time-programmable memory Crypto hardware accelerators for fast secure boot/IP protection memDMA encryption/decryption for fast run-time security Low-cost packaging 184-Ball CSP_BGA package (12 mm × 12mm × 0.8mm pitch), RoHS compliant Low system power with < 100 mW at 400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION

Single-core SHARC+ (w/384KB L1), arm Cortex-A5, 1MB Shared L2, 10/100 Ethernet, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed arm® Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature rangeMemory Large on-chip L2 SRAM with ECC protection, up to 1 MB One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devicesAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

SmartMesh IP Wireless 802.15.4e System-on-Chip Features: 72-pin 10mm × 10mm QFN package 2.4 GHz, IEEE 802.15.4e System-on-Chip, Complete with Embedded SmartMesh Networking Software >99.999% Network Reliability in the Most Challenging RF Environments Sub 50µA Routing Nodes Serves as either a Wireless Mote, EManager, or Access Point Mote in a SmartMesh IP network These products contain encryption. Import/export restrictions may apply.

The ADSP-2136x SHARC® processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices, Inc., Super Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2136x are 32-/40-bit floating-point processors optimized for high performance automotive audio applications. They contain a large on-chip SRAM and ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI).As shown in the functional block diagram on Page 1, the ADSP-2136x uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of signal processing algorithms. With its SIMD computational hardware, the ADSP-2136x can perform two GFLOPS running at 333 MHz. 

The third generation of SHARC® Processors offers increased performance, audio and application-focused peripherals, and new memory configurations. The ADSP-21369 increases performance to 400MHz while simplifying algorithm development with the integration of a high-bandwidth and very flexible external memory interface. The ADSP-21369 is based on a single-instruction, multiple-data (SIMD) core which supports both 32-bit fixed-point and 32-/40-bit floating point arithmetic formats and is completely code-compatible with all prior SHARC Processors allowing for maximum reuse of legacy code.The ADSP-21369 increases the amount of on-chip memory to 2Mb SRAM and 6Mb ROM while integrating a variety of audio-specific and general purpose peripherals. Peripherals such as an all digital S/PDIF transmitter/receiver, 8-channel asynchronous sample rate converter, 8 high-speed serial ports, 4 precision clock generators, and multiple serial interfaces combine to ensure the ADSP-21369 maximizes system throughput while minimizing system bill of materials costs.

The ADSP-BF525C offers up to 600 MHz performance and up to 1200 MMACs. This processor core is supported by an advanced DMA controller supporting one-and two-dimensional DMA transfers between on-chip memory, off-chip memory, and system peripherals. The combination of the processor core speed and the DMA controller allows for efficient processing of audio, voice, video, and image data.The ADSP-BF525C provides peripheral flexibility to complement its high performance processing. The HS USB OTG host direct memory access (HDMA) and NAND flash controller are just a few of the peripheral options on the ADSP-BF525C family—not to mention the availability of up to 48 GPIO ports.For applications where product differentiation represents a challenge for securing market leadership, the ADSP-BF525C enables developers to provide features and benefits to augment their product offerings without compromising cost or power. The scalability of the ADSP-BF525C makes it an ideal candidate for Premium Audio Players where differentiation of features can be realized without sacrificing system cost. Where the diversity of Multimedia applications and content security are key attributes the ADSP-BF525C provides processing flexibility and Lockbox™ Secure Technology to enable users to develop freely and without bounds.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF525C provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.For space constrained audio applications the ADSP-BF525C supports an embedded low power stereo audio CODEC.

The high performance 16/32-bit Blackfin embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the dynamic power management (DPM) functionality allow system designers a flexible platform to address a wide range of portable applications, including consumer, communications and industrial/instrumentation.With the combination of peripherals which enable glue-less connectivity to networked devices such as Ethernet or WiFi 802.11 a/b/g modules and power efficient signal processing, the ADSP-BF527 is well suited to IP connected applications such as VoIP Phone or IP Camera.The VoIP challenge to the embedded-system designer is to choose a processing solution that is cost-effective, easy to deploy and scaleable in performance across market spaces. A “sweet spot” embedded-solution approach is to design with a platform that can implement a low channel count basic VoIP solution, yet retain sufficient capacity for value added capabilities and services – such as video, music, imaging and system control. Unlike traditional VoIP embedded solutions that utilize two processor cores to provide VoIP functionality, the ADSP-BF527 provides a convergent solution in a unified core architecture that allows voice and video signal processing concurrent with RISC MCU processing to handle network and user-interface demands. This unique ability to offer full VoIP functionality on a single convergent processor provides for a unified software development environment, faster system debugging and deployment, and lower overall system cost.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF527 provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.

The ADSP-BF533 provides a high performance, power-efficient processor choice for today's most demanding convergent signal processing applications. The high performance 16-bit/32-bit Blackfin® embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the dynamic power management (DPM) functionality allow system designers a flexible platform to address a wide range of applications including consumer,communications, automotive, and industrial/instrumentation.Architectural Features High performance 16-bit/32-bit embedded processor core 10-stage RISC MCU/DSP pipeline with mixed 16-bit/32-bit ISA for optimal code density Full SIMD architecture, including instructions for accelerated video and image processing Memory management unit (MMU) supporting full memory protection for an isolated and secure environmentHigh Level of Integration Up to 148 kB of on-chip SRAM Glueless video capture and display port Two dual-channel, full-duplex, synchronous serial ports supporting eight stereo I2S channels 12 DMA channels supporting one- and two-dimensional data transfers Memory controller providing glueless connection to multiple banks of external SDRAM, SRAM, Flash, or ROM 160-ball mini-BGA, 169-ball PBGA packages Industrial temperature ranges (40°C to 85°C) and commercial temperature ranges (0°C to 70°C) available

The ADSP-BF533 provides a high performance, power-efficient processor choice for today's most demanding convergent signal processing applications. The high performance 16-bit/32-bit Blackfin® embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the dynamic power management (DPM) functionality allow system designers a flexible platform to address a wide range of applications including consumer,communications, automotive, and industrial/instrumentation.Architectural Features High performance 16-bit/32-bit embedded processor core 10-stage RISC MCU/DSP pipeline with mixed 16-bit/32-bit ISA for optimal code density Full SIMD architecture, including instructions for accelerated video and image processing Memory management unit (MMU) supporting full memory protection for an isolated and secure environmentHigh Level of Integration Up to 148 kB of on-chip SRAM Glueless video capture and display port Two dual-channel, full-duplex, synchronous serial ports supporting eight stereo I2S channels 12 DMA channels supporting one- and two-dimensional data transfers Memory controller providing glueless connection to multiple banks of external SDRAM, SRAM, Flash, or ROM 160-ball mini-BGA, 169-ball PBGA packages Industrial temperature ranges (40°C to 85°C) and commercial temperature ranges (0°C to 70°C) available