The AD8197 is an HDMI™/DVI switch featuring equalized TMDS® inputs and pre-emphasized TMDS outputs, ideal for systems with long cable runs. Outputs can be set to a high impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-OR technique. Flexible channel bundling modes (for both the TMDS channels and the auxiliary signals) allow the AD8197 to be configured as a 4:1 single HDMI/DVI link switch, a dual 8:1 switch, or a single 16:1 switch.The AD8197 is provided in a 100-lead LQFP, Pb-free, surface-mount package, specified to operate over the −40°C to +85°C temperature range. ul { margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:15px; padding-top:0px; padding-right:0px; padding-bottom:10px; padding-left:0px;} li { padding-top:0px; padding-right:0px; padding-bottom:5px; padding-left:0px; margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:0px;} ol { margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:25px; padding-top:0px; padding-right:0px; padding-bottom:10px; padding-left:0px;} li { padding-top:0px; padding-right:0px; padding-bottom:5px; padding-left:0px; margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:0px;}Product Highlights Supports data rates up to 2.25 Gbps, enabling 1080p deep color (12-bit color) HDMI formats, and greater than UXGA (1600 × 1200) DVI resolutions. Input cable equalizer enables use of long cables at the input (more than 20 meters of 24 AWG cable at 2.25 Gbps). Auxiliary switch routes a DDC bus and two additional signals for a single-chip, HDMI 1.3 receive-compliant solution.Applications Multiple input displays Projectors A/V receivers Set-top boxes Advanced television (HDTV) sets Data Sheet, Rev. 0, 1/07

The fourth generation of SHARC® Processors, which includes the ADSP-21469, offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21469 offers the highest performance – 450 MHz/2700 MFLOPs -- within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21469 particularly well suited to address the increasing requirements of the professional and automotive audio market segments. In addition to its higher core performance, the ADSP-21469 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to faster external memory by providing a glueless interface to 16-bit wide DDR2 SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The high performance 16/32-bit Blackfin embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the dynamic power management (DPM) functionality allow system designers a flexible platform to address a wide range of portable applications, including consumer, communications and industrial/instrumentation.With the combination of peripherals which enable glue-less connectivity to networked devices such as Ethernet or WiFi 802.11 a/b/g modules and power efficient signal processing, the ADSP-BF526 is well suited to IP connected applications such as VoIP Phone or IP Camera.The VoIP challenge to the embedded-system designer is to choose a processing solution that is cost-effective, easy to deploy and scaleable in performance across market spaces. A “sweet spot” embedded-solution approach is to design with a platform that can implement a low channel count basic VoIP solution, yet retain sufficient capacity for value added capabilities and services – such as video, music, imaging and system control. Unlike traditional VoIP embedded solutions that utilize two processor cores to provide VoIP functionality, the ADSP-BF526 provides a convergent solution in a unified core architecture that allows voice and video signal processing concurrent with RISC MCU processing to handle network and user-interface demands. This unique ability to offer full VoIP functionality on a single convergent processor provides for a unified software development environment, faster system debugging and deployment, and lower overall system cost.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF526 provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.

Digital Signal Processors & Controllers - DSP, DSC 16-Bit 25MIPS 5V 2 Serial Ports

The DC9021B SmartMesh IP™ Starter Kit provides all the tools for evaluating SmartMesh® network performance with respect to your application needs, including high reliability, ultralow power, scalability and ease of installation. This accelerates device integration and application software development. The DC9021B Starter Kit includes five motes, or nodes (DC9018B-B), to enable you to quickly deploy a multi-hop mesh network in the RF environment specific to your application. The command line interface allows you to quickly see the list of mesh nodes in the network, as well as key performance statistics such as data reliability and latency. The DC9018B-B Evaluation/Development Mote Modules feature easy-to-probe signal pins. In addition, the starter kit provides access to both manager and mote software application programming interfaces (APIs) over USB to enable application software development. The DC2274A-A USB Embedded Network Manager comes factory-configured as an embedded network manager, where both the wireless-to-wired access point function and the network management algorithms run on board. The DC2274A-B USB Access Point Mote enables customers to evaluate VManager, which supports thousands of nodes. SmartMesh IP Starter Kit – includes the following items: One USB Embedded Network Manager (DC2274A-A) One USB Access Point Mote (DC2274A-B) Five Evaluation / Development Motes (DC9018B-B) One Eterna Interface Card (DC9006A), which includes a DC9004 adapter card One Eterna QuikEval Adapter (DC9005A) Additional CR2032 batteries USB Cables Watch the SmartMesh IP Starter kit Video The DC9021B Starter Kit operates in the 2.4000GHz to 2.4835GHz international license-free frequency band. Starter kits and demo boards are for evaluation purposes only. It remains the customer’s responsibility to verify proper and reliable operation in the actual end application. SmartMesh IP Starter Kit Software Software Utility Description Download Link Serial Mux Software used to connect multiple clients to the manager Download SmartMesh SDK (optional) Software development kit used to interact with the devices’ Application Programming Interface (API) GitHub Repository FTDI driver USB-to-Serial drivers for communication with DC9001, DC9006 boards Download VCP from FTDIchip.com LBR (optional) Low power Border Router software utility and sample code. Python script for mapping SmartMesh IP networks onto an IPv4 network (e.g. Ethernet) Download

The HMC955LC4B is a 1 to 2 Demux designed to support data transmission rates up to 32 Gbps. The demux uses both rising and falling edges of the half-rate clock to sample the data in sequence 01-02 and latches the data on the rising edge into the differential outputs. The demux also has high-speed clock synchronous invert input that allows for scrambling of the data. The HMC955LC4B also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All differential inputs to the HMC955LC4B are CML and terminated on-chip with 50 Ohms to the positive supply, GND, and may be AC or DC coupled. The differential CML outputs are source terminated to 50 Ohms and may also be AC or DC coupled. Outputs can be connected directly to a 50 Ohm ground-terminated system or drive devices with CML logic input. The HMC955LC4B operates from a single -3.3 V supply and is available in a ceramic ROHS-compliant 4x4 mm SMT package.APPLICATIONSSONET OC-192Broadband Test & Measurement EquipmentFPGA Interfacing Circuitry16 G and 32 G Fiber Channel100 Gbit EthernetADC Encoder

The HMC958LC5 is a 4:1 Selector designed to support data transmission rates of up to 14 Gbps and selector port operation up to 14 GHz. The selector routes the differential inputs to either one or both of the desired outputs upon assertion of the appropriately selected port. The HMC958LC5 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All single-ended input signals to the HMC958LC5 are terminated with 50 ??to ground on-chip, and may be either AC or DC coupled. The outputs of the HMC958LC5 may be operated either differentially or single ended. Outputs can be connected directly to a 50 ??terminated system, while DC blocking capacitors may be used if the terminating system is 50 ? to a non-ground DC voltage. The HMC958LC5 operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 5 ? 5 mm SMT package.APPLICATIONS SONET OC-192 and 10 GbE 16G Fiber Channel 4:1 Multiplexer Built-In Test Broadband Test & Measurement

The ADIN1200 is a low power, single-port, 10 Mbps and 100 Mbps Ethernet transceiver with low latency specifications designedfor industrial Ethernet applications.This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and media access control (MAC) interface and control logic to manage the reset, clock control and pin configuration.The ADIN1200 is available in a 5 mm ? 5 mm, 32-lead leadframe chip scale package (LFCSP) and can operate with a single3.3 V supply, assuming the use of a 3.3 V MAC interface supply.For maximum flexibility in system level design, a separate VDDIOsupply enables the management data input/output (MDIO) andMAC interface supply voltages to be configured independentlyof the other circuitry on the ADIN1200 allowing operation at1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1200 is held inhardware reset until each of the supplies has crossed its minimumrising threshold value and the power is considered good. Brownoutprotection is provided by monitoring the supplies to detect ifone or more of them drops below a minimum falling thresholdand holding the device in hardware reset until the power suppliesreturn and satisfy the power-on-reset (POR) circuit.The MII management interface (also referred to as MDIOinterface) provides a 2-wire serial interface between a hostprocessor or MAC and the ADIN1200, allowing access tocontrol and status information in the PHY core managementregisters. The interface is compatible with both IEEE? 802.3?Standard Clause 22 and Clause 45 management framestructures.The ADIN1200 can support cable lengths up to 180 meters.Note that throughout this data sheet, multifunction pins, such as XTAL_I/CLK_IN/REF_CLK, are referred to either by the entire pin name or by a single function of the pin, for example, XTAL_I, when only that function is relevant.Applications Industrial automation Process control Factory automation Robotics and motion Control Building automation Test and Measurement Industrial internet of things (IoT)

The ADIN1300 is a low power, single port, Gigabit Ethernet transceiver with low latency and power consumption specifications primarily designed for industrial Ethernet applications.This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and MAC interface and control logic to manage the reset and clock control and pin configuration.The ADIN1300 is available in a 6 mm ? 6 mm, 40-lead lead frame chip scale package (LFCSP). The device operates with a minimum of 2 power supplies, 0.9 V and 3.3 V, assuming the use of a 3.3 V MAC interface supply. For maximum flexibility in system level design, a separate VDDIO supply enables the management data input/output (MDIO) and MAC interface supply voltages to be configured independently of the other circuitry on the ADIN1300, allowing operation at 1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1300 is held in hardware reset until each of the supplies has crossed its minimum rising threshold value. Brown-out protection is provided by monitoring the supplies to detect if one or more supply drops below a minimum falling threshold (see Table 17 on the datasheet), and holding the device in hardware reset until the power supplies return and satisfy the power-on reset (POR) circuit.The MII management interface (also referred to as MDIO interface) provides a 2-wire serial interface between a host processor or MAC (also known as management station (STA)) and the ADIN1300, allowing access to control and status information in the PHY core management registers. The interface is compatible with both the IEEE 802.3 Standard Clause 22 and Clause 45 management frame structures.The ADIN1300 can support cable lengths up to 150 meters at Gigabit speeds and 180 meters when operating at 100 Mbps or 10 Mbps.Applications Industrial automation Process control Factory automation Robotics/Motion Control Building automation Test and Measurement Industrial IoT

The DC2274A-B USB dongle demo board which serves as an Access Point Mote, connecting a SmartMesh IP™ wireless sensor network with a VManager network manager. VManager is a software-based manager that enables: Large Networks – thousands of nodes Increased Bandwidth through Multiple Access Points Hot Failover Gateway Redundancy The DC2274A-B SmartMesh IP USB Manager incorporates the LTP5902-IPM SmartMesh IP Module, pre-programmed with SmartMesh IP Access Point Mote software. It provides a USB connection for both power and software access to the Access Point Mote API UART and CLI UART ports.The DC2274A-B is available individually or as part of the DC9021B SmartMesh IP Starter Kit, which includes five wireless mesh nodes. With a SmartMesh IP Starter Kit, a user can setup a wireless mesh network in minutes and quickly evaluate the network performance in their own application environment.