Dual-core SHARC+ DSP (w/768KB L1), 1MB Shared L2, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature range Memory Large on-chip L2 SRAM with ECC protection, up to 1 MBAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

High Performance Convergent Multimedia Blackfin Processor Features: Lockbox™ Secure Technology: Hardware-enabled security for code and content protection. Two independent DMA controllers Multimedia: Multiple Enhanced Parallel Peripheral Interfaces (EPPI), Pixel Compositor hardware accelerator Human Interface: 18/24-bit LCD Controller 32-bit Up/Down counter / Thumbwheel interface, 8x8 Keypad interface Blackfin® Processor Core with up to 533Mhz (1066 MMACS) performance Connectivity: High Speed USB OTG , Host DMA, UARTs, SPORTs, SPI, TWI, and CAN Expansion: SD/SDIO and ATAPI-6 Controllers Synchronous interface for DDR or Mobile DDR connectivity (See data sheet ordering guide for specific product information) Asynchronous memory interface for SRAM, EEPROM, NAND/NOR, Flash connectivity

Low Power 200MHz Blackfin+ Embedded Processor with 128KByte L2 SRAM & DDR2/LPDDR Interface Features: Blackfin+ core with up to 200 MHz performance Dual 16-bit or single 32-bit MAC support per cycle 16-bit complex MAC and many other instruction set enhancements Instruction set compatible with previous Blackfin product On-Chip Memory 136KB L1 SRAM with multi-parity-bit protection (64KB instruction, 64KB data, 8KB scratchpad) 128KByte on-chip L2 SRAM with ECC protection 512KByte On-chip L2 ROM L3 interface providing 16-bit interface to DDR2 or LPDDR SDRAM devices (up to 200 MHz) Key Peripherals include USB2.0 HS OTG 2x CAN2.0B ePPI Video I/O 2x SPORTs (w/I2S) 2xQuad-SPI / 1xDual-SPI (w/ Host mode option) I2C 2xUART SD/SDIO/MMC (8-bit) 4-ch 12-bit 1MSPS ADC Security and one-time-programmable memory Crypto hardware accelerators for fast secure boot/IP protection memDMA encryption/decryption for fast run-time security Low-cost packaging 184-Ball CSP_BGA package (12 mm × 12mm × 0.8mm pitch), RoHS compliant Low system power with < 53 mW at 200 MHz at 25°C TJUNCTION

240MHz ARM Cortex-M4 with 13+ ENOB ADC, BGA212 Features: Dual 16 bit SAR ADCs with no missing codes, 13+ ENOB, 380ns conversion speed for high precision closed loop control. 240 MHz ARM Cortex M4 Core with Floating Point Unit to support advanced programming models and complex algorithms. 384KB SRAM and 2MB flash memory for large program size. Advanced PWM and timer functions for improved torque ripple and motor performance. SINC filters for glueless connection to AD74xx isolated converters. Harmonic Analysis Engine for compliant grid connection. Ethernet and USB to support networked interfaces. Two CAN interfaces, three UARTS, two SPIs, two SPORTs, eight 32-bit timers, two two-wire interfaces and four quadrature encoder interfaces. 16 bit asynchronous memory bus for external SRAM or FPGA interfacing. 212-ball, 19x19mm CSP_BGA package Up to 105C ambient operating temperature for support of industrial applications.

Single-core SHARC+ (w/384KB L1), arm Cortex-A5, 1MB Shared L2, 10/100 Ethernet, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed arm® Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature rangeMemory Large on-chip L2 SRAM with ECC protection, up to 1 MB One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devicesAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

RapID Platform Generation 2 (RPG2) Network Interface Features: Configurable industrial protocol support PROFINET RT (Class B) PROFINET IRT (Class C): coming soon EtherNet/IP with DLR EtherCAT All protocols precertified Configurable applications processor interface UART: 115,200 bps to 1,000,000 bps Ethernet at 10 Mbps or 100 Mbps SPI follower: 10 MHz maximum clock I2C, QSPI, and CAN: future option Industrial Ethernet interface-compliant to IEEE 802.3, 10Base or 100Base transmit half and full duplex Single 3.3 V power supply, 840 mW Cycle time down to 1 ms (cycle times vary based on protocol, link type, and application data) 194-ball chip-scale package BGA form factor RoHS 3 compliant –40°C to +85°C industrial temperature range

RapID Platform Generation 2 (RPG2) Network Interface Features: Configurable industrial protocol support PROFINET RT (Class B) PROFINET IRT (Class C): coming soon EtherNet/IP with DLR EtherCAT All protocols precertified Configurable applications processor interface UART: 115,200 bps to 1,000,000 bps Ethernet at 10 Mbps or 100 Mbps SPI follower: 10 MHz maximum clock I2C, QSPI, and CAN: future option Industrial Ethernet interface-compliant to IEEE 802.3, 10Base or 100Base transmit half and full duplex Single 3.3 V power supply, 840 mW Cycle time down to 1 ms (cycle times vary based on protocol, link type, and application data) 194-ball chip-scale package BGA form factor RoHS 3 compliant –40°C to +85°C industrial temperature range

Configurable Impedance Network Analyzer & Potentiostat with Integrated Cortex M3 Core Features: Analog performance 160 kSPS, 16-bit, precision analog-to-digital converter (ADC) 4 dedicated voltage measurement channels 8 current measurement channels Impedance measurement engine High precision voltage reference Supply noise rejection filtering Ultralow leakage configurable switch matrix 12-bit digital-to-analog converter (DAC) Precision instrumentation amplifier control loop 6-channel CapTouch controller Temperature sensor Analog hardware accelerators Autonomous analog front-end (AFE) controller Independent sequencer for AFE functions Direct digital synthesizer (DDS)/arbitrary waveform generator Receive filters Complex impedance measurement (DFT) engine Processing 16 MHz ARM Cortex-M3 processor 384 kB of embedded flash memory 32 kB system SRAM 16 kB Flash configured EEPROM Integrated full-speed USB 2.0 controller and PHY Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Real-time clock (RTC) General-purpose, wake-up, and watchdog timers Communication Input/output I2S and beeper interface LCD display controller (parallel and serial) LCD segment controller SPI, I2C, and UART peripheral interfaces Programmable GPIOs Power Coin cell battery compatible 2.5 V to 3.6 V active measurement range Power management unit (PMU) Power-on reset (POR) and power supply monitor (PSM) Packages and temperature range Operating temperature range: −40°C to +85°C Package: 120-lead, 8 mm × 8 mm CSP_BGA 

Configurable Impedance Network Analyzer & Potentiostat with Integrated Cortex M3 Core Features: Analog performance 160 kSPS, 16-bit, precision analog-to-digital converter (ADC) 4 dedicated voltage measurement channels 8 current measurement channels Impedance measurement engine High precision voltage reference Supply noise rejection filtering Ultralow leakage configurable switch matrix 12-bit digital-to-analog converter (DAC) Precision instrumentation amplifier control loop 6-channel CapTouch controller Temperature sensor Analog hardware accelerators Autonomous analog front-end (AFE) controller Independent sequencer for AFE functions Direct digital synthesizer (DDS)/arbitrary waveform generator Receive filters Complex impedance measurement (DFT) engine Processing 16 MHz ARM Cortex-M3 processor 384 kB of embedded flash memory 32 kB system SRAM 16 kB Flash configured EEPROM Integrated full-speed USB 2.0 controller and PHY Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Real-time clock (RTC) General-purpose, wake-up, and watchdog timers Communication Input/output I2S and beeper interface LCD display controller (parallel and serial) LCD segment controller SPI, I2C, and UART peripheral interfaces Programmable GPIOs Power Coin cell battery compatible 2.5 V to 3.6 V active measurement range Power management unit (PMU) Power-on reset (POR) and power supply monitor (PSM) Packages and temperature range Operating temperature range: −40°C to +85°C Package: 120-lead, 8 mm × 8 mm CSP_BGA 

3.3 V, 200 Mbps, Half-Duplex, High Speed M-LVDS Transceiver with Type 2 Receiver Features: Multipoint LVDS transceivers (low voltage differential signaling driver and receiver pairs) Switching rate: 200 Mbps (100 MHz) Supported bus loads: 30 to 55 Type 2 receiver type: threshold offset of 100 mV for open-circuit and bus-idle fail-safe Conforms to TIA/EIA-899 standard for M-LVDS Glitch free power-up/power-down on M-LVDS bus Controlled transition times on driver output Common-mode range: −1 V to +3.4 V, allowing communication with 2 V of ground noise Driver outputs high-Z when disabled or powered off See data sheet for additional features