The ADSP-BF531 / ADSP-BF532 / ADSP-BF533 processors are members of the Blackfin® family of products, incorporating the Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities into a single instruction set architecture. The ADSP-BF531 / ADSP-BF532 / ADSP-BF533 processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1.PERIPHERALS Parallel peripheral interface PPI, supporting ITU-R 656 video data formats 2 dual-channel, full duplex synchronous serial ports, supporting eight stereo I2S channels 2 memory-to-memory DMAs 8 peripheral DMAs SPI-compatible port Three 32-bit timer/counters with PWM support Real-time clock and watchdog timer 32-bit core timer Up to 16 general-purpose I/O pins (GPIO) UART with support for IrDA Event handler Debug/JTAG interface On-chip PLL capable of frequency multiplication

The Blackfin® Processor family expands the performance envelope with the ADSP-BF561. With two high performance Blackfin Processor cores, flexible cache architecture, enhanced DMA subsystem, and Dynamic Power Management (DPM) functionality, the ADSP-BF561 can support complex control and signal processing tasks while maintaining extremely high datathroughput.The ADSP-BF561 is a functional extension of the popular Blackfin Processor family and is ideally suited for a broad range of industrial, instrumentation, medical, and consumer appliance applications—allowing for scalability based upon the required data bandwidth and mix of control, plus signal processing needed in the end product.High-Level of Integration 328 KBytes of on-chip memory configured as: 32 KBytes of L1 instruction memory SRAM/Cache per core 64 KBytes of L1 data memory SRAM/Cache per core 4 KBytes of L1 scratchpad memory per core 128 KBytes of low-latency shared L2 memory 32-bit Memory Controller providing glueless connection to multiple banks of SDRAM, SRAM, Flash or ROM. Two Parallel Peripheral Interfaces Units supporting ITU-R 656 video data formats. Two dual-channel, full-duplex, synchronous serial ports supporting eight stereo I2S channels. Dual 16 Channel DMA Controllers, supporting one and two-dimension transfers. SPI-compatible Port. UART with support for IrDA®. 12 timer/counters supporting PWM, pulsewidth and event count modes. 48 Programmable Flags/General Purpose I/O. Event Handler. Dual Watchdog timers. PLL capable of 1x to 63x frequency multiplication. 256-ball Mini-BGA and 297-ball Sparse PBGA packages.

The ADSP-BF608 Blackfin processor is optimized for embedded vision and video analytics applications using a dual-core fixed-point DSP processor with a unique pipelined vision processor (PVP). The PVP is a set of functional blocks next to the Blackfin cores designed to accelerate image processing algorithms and reduce overall bandwidth requirements.Other features include a high performance enhanced infrastructure, large on-chip memory and a feature rich peripheral set with expanded connectivity options. In addition to these the ADSP-BF608 processor contains features for safety-critical applications, including a CRC for memory protection, Parity and ECC protection in the internal memory blocks and a Fault Management Unit.The ADSP-BF608 processor is ideal for many embedded vision applications such as automotive advanced driver assistance systems (ADAS), machine vision and robotics for industrial manufacturing systems, security and surveillance system analytics and bar code scanners.

Metering Systems on a Chip - SoC Residential Energy Meter IC

ANALOG DEVELOPMENT KIT ACCESSORIES;

DEBUGGERS, EMULATORS & JTAG TOOLS;

High-Performance 32-bit Floating-Point SHARC Processor for General Purpose Applications Features: 400MHz SIMD SHARC Core, capable of 2.4 GFLOPS peak performance 2Mbits SRAM; 6 Mbits customer-definable ROM High bandwidth, 32-bit external memory interface supporting glue-less interface to SDRAM, SRAM, and FLASH Digital Audio Interface (DAI) enabling user-definable access to system peripherals including 8 serial ports (SPORTs), S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and 4 precision clock generators. Digital Peripheral Interface (DPI) enabling user-definable access to system peripherals including 2 SPI-compatible ports, 2 UARTs, 3 full-featured timers, and a two-wire interface compliant to the I2C standard. 34 zero-overhead DMA channels 16 Pulse Width Modulation (PWM) channels 208-lead LQFP-EP and 256-ball SBGA packages Commercial and industrial temperature ranges Maximum core performance is reduced for LQFP package

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 800MHz SHARC+ DSP with 640KB L1, 512KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 600MHz (max) or 800MHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 512KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications