Configurable Impedance Network Analyzer & Potentiostat with Integrated Cortex M3 Core Features: Analog performance 160 kSPS, 16-bit, precision analog-to-digital converter (ADC) 4 dedicated voltage measurement channels 8 current measurement channels Impedance measurement engine High precision voltage reference Supply noise rejection filtering Ultralow leakage configurable switch matrix 12-bit digital-to-analog converter (DAC) Precision instrumentation amplifier control loop 6-channel CapTouch controller Temperature sensor Analog hardware accelerators Autonomous analog front-end (AFE) controller Independent sequencer for AFE functions Direct digital synthesizer (DDS)/arbitrary waveform generator Receive filters Complex impedance measurement (DFT) engine Processing 16 MHz ARM Cortex-M3 processor 384 kB of embedded flash memory 32 kB system SRAM 16 kB Flash configured EEPROM Integrated full-speed USB 2.0 controller and PHY Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Real-time clock (RTC) General-purpose, wake-up, and watchdog timers Communication Input/output I2S and beeper interface LCD display controller (parallel and serial) LCD segment controller SPI, I2C, and UART peripheral interfaces Programmable GPIOs Power Coin cell battery compatible 2.5 V to 3.6 V active measurement range Power management unit (PMU) Power-on reset (POR) and power supply monitor (PSM) Packages and temperature range Operating temperature range: −40°C to +85°C Package: 120-lead, 8 mm × 8 mm CSP_BGA 

Configurable Impedance Network Analyzer & Potentiostat with Integrated Cortex M3 Core Features: Analog performance 160 kSPS, 16-bit, precision analog-to-digital converter (ADC) 4 dedicated voltage measurement channels 8 current measurement channels Impedance measurement engine High precision voltage reference Supply noise rejection filtering Ultralow leakage configurable switch matrix 12-bit digital-to-analog converter (DAC) Precision instrumentation amplifier control loop 6-channel CapTouch controller Temperature sensor Analog hardware accelerators Autonomous analog front-end (AFE) controller Independent sequencer for AFE functions Direct digital synthesizer (DDS)/arbitrary waveform generator Receive filters Complex impedance measurement (DFT) engine Processing 16 MHz ARM Cortex-M3 processor 384 kB of embedded flash memory 32 kB system SRAM 16 kB Flash configured EEPROM Integrated full-speed USB 2.0 controller and PHY Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Real-time clock (RTC) General-purpose, wake-up, and watchdog timers Communication Input/output I2S and beeper interface LCD display controller (parallel and serial) LCD segment controller SPI, I2C, and UART peripheral interfaces Programmable GPIOs Power Coin cell battery compatible 2.5 V to 3.6 V active measurement range Power management unit (PMU) Power-on reset (POR) and power supply monitor (PSM) Packages and temperature range Operating temperature range: −40°C to +85°C Package: 120-lead, 8 mm × 8 mm CSP_BGA 

ANALOG DEVELOPMENT KIT ACCESSORIES;

DEBUGGERS, EMULATORS & JTAG TOOLS;

High-Performance 32-bit Floating-Point SHARC Processor for General Purpose Applications Features: 400MHz SIMD SHARC Core, capable of 2.4 GFLOPS peak performance 2Mbits SRAM; 6 Mbits customer-definable ROM High bandwidth, 32-bit external memory interface supporting glue-less interface to SDRAM, SRAM, and FLASH Digital Audio Interface (DAI) enabling user-definable access to system peripherals including 8 serial ports (SPORTs), S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and 4 precision clock generators. Digital Peripheral Interface (DPI) enabling user-definable access to system peripherals including 2 SPI-compatible ports, 2 UARTs, 3 full-featured timers, and a two-wire interface compliant to the I2C standard. 34 zero-overhead DMA channels 16 Pulse Width Modulation (PWM) channels 208-lead LQFP-EP and 256-ball SBGA packages Commercial and industrial temperature ranges Maximum core performance is reduced for LQFP package

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 800MHz SHARC+ DSP with 640KB L1, 512KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 600MHz (max) or 800MHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 512KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Dual-core SHARC+ DSP (w/768KB L1), 1MB Shared L2, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature range Memory Large on-chip L2 SRAM with ECC protection, up to 1 MBAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

High Performance Convergent Multimedia Blackfin Processor Features: Lockbox™ Secure Technology: Hardware-enabled security for code and content protection. Two independent DMA controllers Multimedia: Multiple Enhanced Parallel Peripheral Interfaces (EPPI), Pixel Compositor hardware accelerator Human Interface: 18/24-bit LCD Controller 32-bit Up/Down counter / Thumbwheel interface, 8x8 Keypad interface Blackfin® Processor Core with up to 533Mhz (1066 MMACS) performance Connectivity: High Speed USB OTG , Host DMA, UARTs, SPORTs, SPI, TWI, and CAN Expansion: SD/SDIO and ATAPI-6 Controllers Synchronous interface for DDR or Mobile DDR connectivity (See data sheet ordering guide for specific product information) Asynchronous memory interface for SRAM, EEPROM, NAND/NOR, Flash connectivity