The ADSP-21587 processor is part of the new, high-performance, power-efficient, real-time series that delivers greater than 24 giga-floating-point operations per second using two enhanced SHARC+® cores and advanced DSP accelerators (FFT, FIR, IIR). The ADSP-SC58x and ADSP-2158x series consume less than 2 watts, making the new processor line-up more than 5x more power efficient than previous SHARC products. This advantage provides industry leading digital signal processing performance for applications where thermal management sets the limit for power consumption, or where the higher costs and lower reliability of fans cannot be tolerated.  Applications include automotive, consumer and professional audio, multi-axis motor control, and energy distribution systems.The ADSP-2158x family is designed for applications where a DSP co-processor is exclusively needed and includes two SHARC+ cores and a peripheral set matched to a DSP core.  The new, code-compatible, enhanced SHARC+ core features clock-rate and power-efficiency improvements and adds instruction/data cache options, native double-precision floating-point support, and a number of other new instructions. Designed for low-power and using a low-leakage CMOS process, the ADSP-SC58x/2158x families deliver 500 MHz with 105°C environments in mind and provide a roadmap to future implementations at higher performance. More than 1.5 Mbytes of fast on-chip SRAM and up to two DDR3/2/LP interfaces aid efficient real-time performance while the memory subsystem includes major enhancements with advanced DMA engines for simultaneous data transfer.With software IP protection a growing industry security concern, ARM® TrustZone® security and an onboard crypto hardware accelerators are included. For applications where reliability is a critical requirement, memory parity and error-correction hardware provide higher data integrity. The overall integration and low-power features offered by the new ADSP-SC58x and ADSP-2158x series deliver significant BOM and board area savings and provide lower design complexity and reduced time to market for today’s complex applications.The ADSP-SC58x/2158x  is supported by ADI’s award winning Crosscore®  Embedded Studio development tool suite, providing design engineers with interactive, real-time development tools that help optimize their design and speed time to market.Additionally, ADI and Micrium have collaborated to offer µC/OS-II® & µC/OS-III® real-time kernels on SHARC+.The compatible ADSP-SC589 EZ-KIT-Lite development board and ICE-1000/2000 emulators facilitate the creation, test, and debug of advanced applications. Working in tandem with CrossCore Embedded Studio, the emulators provide state-of-the-art support for all JTAG-compliant Analog Devices processors now utilizing CoreSight™ from ARM.

The ADSP-SC589 processor is part of the new, high-performance, power-efficient, real-time series that delivers greater than 24 giga-floating-point operations per second using two enhanced SHARC+® cores and advanced DSP accelerators (FFT, FIR, IIR). The ADSP-SC58x and ADSP-2158x series consume less than 2 watts, making the new processor line-up more than 5x more power efficient than previous SHARC products. This advantage provides industry leading digital signal processing performance for applications where thermal management sets the limit for power consumption, or where the higher costs and lower reliability of fans cannot be tolerated.  Applications include automotive, consumer and professional audio, multi-axis motor control, and energy distribution systems.The ADSP-SC58x products complement the SHARC+ cores and DSP accelerators with the addition of an ARM® Cortex-A5 processor, with FPU and Neon® DSP extensions to handle additional real-time processing tasks and manage peripherals used to interface to time-critical data in audio, industrial closed-loop control, and industrial sensing applications. These interfaces includes Gigabit Ethernet, USB High-Speed, mobile storage (including SD/SDIO), PCI Express and a rich variety of other connectivity options for a flexible and simplified system design.The ADSP-2158x family is designed for applications where a DSP co-processor is exclusively needed and includes two SHARC+ cores and a peripheral set matched to a DSP core.The new, code-compatible, enhanced SHARC+ core features clock-rate and power-efficiency improvements and adds instruction/data cache options, native double-precision floating-point support, and a number of other new instructions. Designed for low-power and using a low-leakage CMOS process, the ADSP-SC58x/2158x families deliver 500 MHz with 105°C environments in mind and provide a roadmap to future implementations at higher performance. More than 1.8 Mbytes of fast on-chip SRAM and up to two DDR3/2/LP interfaces aid efficient real-time performance while the memory subsystem includes major enhancements with advanced DMA engines for simultaneous data transfer.With software IP protection a growing industry security concern, ARM® TrustZone® security and an onboard crypto hardware accelerators are included. For applications where reliability is a critical requirement, memory parity and error-correction hardware provide higher data integrity. The overall integration and low-power features offered by the new ADSP-SC58x and ADSP-2158x series deliver significant BOM and board area savings and provide lower design complexity and reduced time to market for today’s complex applications.The ADSP-SC58x/2158x  is supported by ADI’s award winning Crosscore®  Embedded Studio development tool suite, providing design engineers with interactive, real-time development tools that help optimize their design and speed time to market.Additionally, ADI and Micrium have collaborated to offer µC/OS-II® & µC/OS-III® real-time kernels on both SHARC+ and ARM Cortex-A5 cores, as well as Micrium’s USB Host, USB Device and file system stacks running on the ARM Cortex-A5.Analog Devices also provides the Linux Add-In for CrossCore Embedded Studio, a custom Linux board support package based on Buildroot, enabling customers interested in taking advantage of the communication stacks and application packages available for embedded Linux, running on the ARM Cortex-A5 core.  Target Linux availability is September 2015 and to request, please complete the software request form and specify “Linux SC58x Support' in the Additional Comments field.The ADSP-SC589 EZ-KIT-Lite development board and ICE-1000/2000 emulators facilitate the creation, test, and debug of advanced applications. Working in tandem with CrossCore Embedded Studio, the emulators provide state-of-the-art support for all JTAG-compliant Analog Devices processors now utilizing CoreSight™ from ARM.

Metering Systems on a Chip - SoC Sgl Phase AC Pwr Measurement IC

Metering Systems on a Chip - SoC 3-Phase Energy Meter I/C

The ADSP-21160M DSP is a SHARC processor that is optimized for applications such as telephony, medical imaging, radar/sonar electronics, communications, 3D graphics and imaging. The ADSP-21160M features a Single-Instruction-Multiple-Data (SIMD) architecture.Using two computational units (ALU, Barrel Shifter, MAC, Register files), the ADSP-21160M can have a five fold performance increase versus the ADSP-2106x on a range of DSP algorithms. It is code compatible with ADI's popular first generation ADSP-2106x SHARC DSPs. Like other SHARCs, the ADSP-21160M is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160M includes an 80 MHz core for processing both 32-bit fixed-point and (32-bit, 40-bit) floating-point data types, a dual-ported 4 Mbit on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal busses to eliminate I/O bottlenecks.The ADSP-21160M is optimized for multiprocessing topologies; SHARC supports multiprocessing via link ports or an external port. In the diagram below, both cluster and link port multiprocessing is shown. Over the external port up to six 21160Ms may be connected together without any additional support logic. The arbitration for this shared bus is integrated on-chip. Each SHARC in the cluster has access to every SHARC's internal memory. Through the external port connection, optional external memory may be shared as well.The six link ports are another way to gluelessly connect a multiprocessing system. Both, the links and the cluster can be used simultaneously and systems with hundreds of SHARC DSPs can be developed using both peripherals.Maximize Speed, Minimize Size The ADSP-21160M is offered in a 27mm x 27mm 400-ball PBGA (Plastic Ball Grid Array) package 40% smaller than processors in this performance class.More Processing Per WattIn addition to small size and high performance, the 21160M's power dissipation enables new levels of MFLOPS per watt. The ADSP-21160M typical power dissipation is 2 watts, enabling 240 MFLOPS of performance per watt. This allows designers to use multiple processors on a PCI card within the PCI power limit of 25 watts. With eight 21160M DSPs, providing 480 MFLOPS each, a standard PCI card design can obtain 3.84 GFLOPS performance and leave 9 watts for other circuitry.The ADSP-21160M is supported by hundreds of readily available third-party hardware and software products and ADI's powerful VisualDSP++ development system, allowing for fast and easy development, debug and deployment.

The ADL5391 draws on three decades of experience in advanced analog multiplier products. It provides the same general mathematical function that has been field proven to provide an exceptional degree of versatility in function synthesis:VW = α × (VX x VY)/1 V + VZThe most significant advance in the ADL5391 is the use of anew multiplier core architecture, which differs markedly fromthe conventional form that has been in use since 1970. Theconventional structure that employs a current mode, translinearcore is fundamentally asymmetric with respect to the X and Yinputs, leading to relative amplitude and timing misalignmentsthat are problematic at high frequencies. The new multiplier coreeliminates these misalignments by offering symmetric signalpaths for both X and Y inputs. The Z input allows a signal to beadded directly to the output. This can be used to cancel a carrieror to apply a static offset voltage.The fully differential X, Y, and Z input interfaces are operationalover a ±2 V range, and they can be used in single-ended fashion.The user can apply a common mode at these inputs to varyfrom the internally set VPOS/2 down to ground. If these inputsare ac-coupled, their nominal voltage will be VPOS/2. These inputinterfaces each present a differential 500 Ω input impedance up toapproximately 700 MHz, decreasing to 50 Ω at 2 GHz. The gainscaling input, GADJ, can be used for fine adjustment of the gainscaling constant (α) about unity.The differential output can swing ±2 V about the VPOS/2common-mode and can be taken in a single-ended fashion aswell. The output common mode is designed to interface directlyto the inputs of another ADL5391. Light dc loads can be groundreferenced; however, ac-coupling of the outputs is recommendedfor heavy loads.The ENBL pin allows the ADL5391 to be disabled quickly to astandby mode. It operates off supply voltages from 4.5 V to 5.5 Vwhile consuming approximately 130 mA.The ADL5391 is fabricated on Analog Devices, Inc. proprietary,high performance, 65 GHz, SOI complementary, SiGe bipolarIC process. It is available in a 16-lead, RoHS compliant, LFCSPand operates over a −40°C to +85°C temperature range.Evaluation boards are available.Applications Wideband multiplication and summing High frequency analog modulation Adaptive antennas (diversity/phased array) Square-law detectors and true rms detectors Accurate polynomial function synthesis DC capable VGA with very fast control

RapID Platform Generation 2 (RPG2) Network Interface Features: Configurable industrial protocol support PROFINET RT (Class B) PROFINET IRT (Class C): coming soon EtherNet/IP with DLR EtherCAT All protocols precertified Configurable applications processor interface UART: 115,200 bps to 1,000,000 bps Ethernet at 10 Mbps or 100 Mbps SPI follower: 10 MHz maximum clock I2C, QSPI, and CAN: future option Industrial Ethernet interface-compliant to IEEE 802.3, 10Base or 100Base transmit half and full duplex Single 3.3 V power supply, 840 mW Cycle time down to 1 ms (cycle times vary based on protocol, link type, and application data) 194-ball chip-scale package BGA form factor RoHS 3 compliant –40°C to +85°C industrial temperature range

RapID Platform Generation 2 (RPG2) Network Interface Features: Configurable industrial protocol support PROFINET RT (Class B) PROFINET IRT (Class C): coming soon EtherNet/IP with DLR EtherCAT All protocols precertified Configurable applications processor interface UART: 115,200 bps to 1,000,000 bps Ethernet at 10 Mbps or 100 Mbps SPI follower: 10 MHz maximum clock I2C, QSPI, and CAN: future option Industrial Ethernet interface-compliant to IEEE 802.3, 10Base or 100Base transmit half and full duplex Single 3.3 V power supply, 840 mW Cycle time down to 1 ms (cycle times vary based on protocol, link type, and application data) 194-ball chip-scale package BGA form factor RoHS 3 compliant –40°C to +85°C industrial temperature range

High-Performance 32-bit Floating-Point SHARC Processor for General Purpose Applications Features: 400MHz SIMD SHARC Core, capable of 2.4 GFLOPS peak performance 2Mbits SRAM; 6 Mbits customer-definable ROM High bandwidth, 32-bit external memory interface supporting glue-less interface to SDRAM, SRAM, and FLASH Digital Audio Interface (DAI) enabling user-definable access to system peripherals including 8 serial ports (SPORTs), S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and 4 precision clock generators. Digital Peripheral Interface (DPI) enabling user-definable access to system peripherals including 2 SPI-compatible ports, 2 UARTs, 3 full-featured timers, and a two-wire interface compliant to the I2C standard. 34 zero-overhead DMA channels 16 Pulse Width Modulation (PWM) channels 208-lead LQFP-EP and 256-ball SBGA packages Commercial and industrial temperature ranges Maximum core performance is reduced for LQFP package

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications