The ADSP-BF525 offers up to 600 MHz performance and up to 1200 MMACs. This processor core is supported by an advanced DMA controller supporting one-and two-dimensional DMA transfers between on-chip memory, off-chip memory, and system peripherals. The combination of the processor core speed and the DMA controller allows for efficient processing of audio, voice, video, and image data.The ADSP-BF525 provides peripheral flexibility to complement its high performance processing. The HS USB OTG host direct memory access (HDMA) and NAND flash controller are just a few of the peripheral options on the ADSP-BF525 family—not to mention the availability of up to 48 GPIO ports.For applications where product differentiation represents a challenge for securing market leadership, the ADSP-BF525 enables developers to provide features and benefits to augment their product offerings without compromising cost or power. The scalability of the ADSP-BF525 makes it an ideal candidate for Premium Audio Players where differentiation of features can be realized without sacrificing system cost. Where the diversity of Multimedia applications and content security are key attributes the ADSP-BF525 provides processing flexibility and Lockbox™ Secure Technology to enable users to develop freely and without bounds.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF525 provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.

The ADSP-BF525 offers up to 600 MHz performance and up to 1200 MMACs. This processor core is supported by an advanced DMA controller supporting one-and two-dimensional DMA transfers between on-chip memory, off-chip memory, and system peripherals. The combination of the processor core speed and the DMA controller allows for efficient processing of audio, voice, video, and image data.The ADSP-BF525 provides peripheral flexibility to complement its high performance processing. The HS USB OTG host direct memory access (HDMA) and NAND flash controller are just a few of the peripheral options on the ADSP-BF525 family—not to mention the availability of up to 48 GPIO ports.For applications where product differentiation represents a challenge for securing market leadership, the ADSP-BF525 enables developers to provide features and benefits to augment their product offerings without compromising cost or power. The scalability of the ADSP-BF525 makes it an ideal candidate for Premium Audio Players where differentiation of features can be realized without sacrificing system cost. Where the diversity of Multimedia applications and content security are key attributes the ADSP-BF525 provides processing flexibility and Lockbox™ Secure Technology to enable users to develop freely and without bounds.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF525 provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.

The ADSP-BF531 / ADSP-BF532 / ADSP-BF533 processors are members of the Blackfin® family of products, incorporating the Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities into a single instruction set architecture. The ADSP-BF531 / ADSP-BF532 / ADSP-BF533 processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1.PERIPHERALS Parallel peripheral interface PPI, supporting ITU-R 656 video data formats 2 dual-channel, full duplex synchronous serial ports, supporting eight stereo I2S channels 2 memory-to-memory DMAs 8 peripheral DMAs SPI-compatible port Three 32-bit timer/counters with PWM support Real-time clock and watchdog timer 32-bit core timer Up to 16 general-purpose I/O pins (GPIO) UART with support for IrDA Event handler Debug/JTAG interface On-chip PLL capable of frequency multiplication

The Blackfin® Processor family expands the performance envelope with the ADSP-BF561. With two high performance Blackfin Processor cores, flexible cache architecture, enhanced DMA subsystem, and Dynamic Power Management (DPM) functionality, the ADSP-BF561 can support complex control and signal processing tasks while maintaining extremely high datathroughput.The ADSP-BF561 is a functional extension of the popular Blackfin Processor family and is ideally suited for a broad range of industrial, instrumentation, medical, and consumer appliance applications—allowing for scalability based upon the required data bandwidth and mix of control, plus signal processing needed in the end product.High-Level of Integration 328 KBytes of on-chip memory configured as: 32 KBytes of L1 instruction memory SRAM/Cache per core 64 KBytes of L1 data memory SRAM/Cache per core 4 KBytes of L1 scratchpad memory per core 128 KBytes of low-latency shared L2 memory 32-bit Memory Controller providing glueless connection to multiple banks of SDRAM, SRAM, Flash or ROM. Two Parallel Peripheral Interfaces Units supporting ITU-R 656 video data formats. Two dual-channel, full-duplex, synchronous serial ports supporting eight stereo I2S channels. Dual 16 Channel DMA Controllers, supporting one and two-dimension transfers. SPI-compatible Port. UART with support for IrDA®. 12 timer/counters supporting PWM, pulsewidth and event count modes. 48 Programmable Flags/General Purpose I/O. Event Handler. Dual Watchdog timers. PLL capable of 1x to 63x frequency multiplication. 256-ball Mini-BGA and 297-ball Sparse PBGA packages.

The ADL5391 draws on three decades of experience in advanced analog multiplier products. It provides the same general mathematical function that has been field proven to provide an exceptional degree of versatility in function synthesis:VW = α × (VX x VY)/1 V + VZThe most significant advance in the ADL5391 is the use of anew multiplier core architecture, which differs markedly fromthe conventional form that has been in use since 1970. Theconventional structure that employs a current mode, translinearcore is fundamentally asymmetric with respect to the X and Yinputs, leading to relative amplitude and timing misalignmentsthat are problematic at high frequencies. The new multiplier coreeliminates these misalignments by offering symmetric signalpaths for both X and Y inputs. The Z input allows a signal to beadded directly to the output. This can be used to cancel a carrieror to apply a static offset voltage.The fully differential X, Y, and Z input interfaces are operationalover a ±2 V range, and they can be used in single-ended fashion.The user can apply a common mode at these inputs to varyfrom the internally set VPOS/2 down to ground. If these inputsare ac-coupled, their nominal voltage will be VPOS/2. These inputinterfaces each present a differential 500 Ω input impedance up toapproximately 700 MHz, decreasing to 50 Ω at 2 GHz. The gainscaling input, GADJ, can be used for fine adjustment of the gainscaling constant (α) about unity.The differential output can swing ±2 V about the VPOS/2common-mode and can be taken in a single-ended fashion aswell. The output common mode is designed to interface directlyto the inputs of another ADL5391. Light dc loads can be groundreferenced; however, ac-coupling of the outputs is recommendedfor heavy loads.The ENBL pin allows the ADL5391 to be disabled quickly to astandby mode. It operates off supply voltages from 4.5 V to 5.5 Vwhile consuming approximately 130 mA.The ADL5391 is fabricated on Analog Devices, Inc. proprietary,high performance, 65 GHz, SOI complementary, SiGe bipolarIC process. It is available in a 16-lead, RoHS compliant, LFCSPand operates over a −40°C to +85°C temperature range.Evaluation boards are available.Applications Wideband multiplication and summing High frequency analog modulation Adaptive antennas (diversity/phased array) Square-law detectors and true rms detectors Accurate polynomial function synthesis DC capable VGA with very fast control

The ADSP-BF608 Blackfin processor is optimized for embedded vision and video analytics applications using a dual-core fixed-point DSP processor with a unique pipelined vision processor (PVP). The PVP is a set of functional blocks next to the Blackfin cores designed to accelerate image processing algorithms and reduce overall bandwidth requirements.Other features include a high performance enhanced infrastructure, large on-chip memory and a feature rich peripheral set with expanded connectivity options. In addition to these the ADSP-BF608 processor contains features for safety-critical applications, including a CRC for memory protection, Parity and ECC protection in the internal memory blocks and a Fault Management Unit.The ADSP-BF608 processor is ideal for many embedded vision applications such as automotive advanced driver assistance systems (ADAS), machine vision and robotics for industrial manufacturing systems, security and surveillance system analytics and bar code scanners.

The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21478 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21478 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21478 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21479 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21479 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21479 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs. Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The SHARC ADSP-21489 is one of two new members of the fourth generation of SHARC® Processors that now includes the ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21489 offers the highest performance–450 MHz/2700 MFLOPs–in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The BF504 is a low cost member of the Blackfin portfolio of processors. With a 400 MHz core clock speed and a unique peripheral set including two three-phase PWM units, an ADC Control Module, two SPI’s, two SPORT’s, a CAN controller, a PPI, eight general purpose counters and a Removable Storage Interface, the BF504 is feature and cost optimized for compute intensive industrial and general purpose applications that do not require external memory or executable flash. The BF504 is offered in a low cost 12 × 12mm LFCSP package in commercial and industrial temperature grades.