The ADSP-SC589 processor is part of the new, high-performance, power-efficient, real-time series that delivers greater than 24 giga-floating-point operations per second using two enhanced SHARC+® cores and advanced DSP accelerators (FFT, FIR, IIR). The ADSP-SC58x and ADSP-2158x series consume less than 2 watts, making the new processor line-up more than 5x more power efficient than previous SHARC products. This advantage provides industry leading digital signal processing performance for applications where thermal management sets the limit for power consumption, or where the higher costs and lower reliability of fans cannot be tolerated.  Applications include automotive, consumer and professional audio, multi-axis motor control, and energy distribution systems.The ADSP-SC58x products complement the SHARC+ cores and DSP accelerators with the addition of an ARM® Cortex-A5 processor, with FPU and Neon® DSP extensions to handle additional real-time processing tasks and manage peripherals used to interface to time-critical data in audio, industrial closed-loop control, and industrial sensing applications. These interfaces includes Gigabit Ethernet, USB High-Speed, mobile storage (including SD/SDIO), PCI Express and a rich variety of other connectivity options for a flexible and simplified system design.The ADSP-2158x family is designed for applications where a DSP co-processor is exclusively needed and includes two SHARC+ cores and a peripheral set matched to a DSP core.The new, code-compatible, enhanced SHARC+ core features clock-rate and power-efficiency improvements and adds instruction/data cache options, native double-precision floating-point support, and a number of other new instructions. Designed for low-power and using a low-leakage CMOS process, the ADSP-SC58x/2158x families deliver 500 MHz with 105°C environments in mind and provide a roadmap to future implementations at higher performance. More than 1.8 Mbytes of fast on-chip SRAM and up to two DDR3/2/LP interfaces aid efficient real-time performance while the memory subsystem includes major enhancements with advanced DMA engines for simultaneous data transfer.With software IP protection a growing industry security concern, ARM® TrustZone® security and an onboard crypto hardware accelerators are included. For applications where reliability is a critical requirement, memory parity and error-correction hardware provide higher data integrity. The overall integration and low-power features offered by the new ADSP-SC58x and ADSP-2158x series deliver significant BOM and board area savings and provide lower design complexity and reduced time to market for today’s complex applications.The ADSP-SC58x/2158x  is supported by ADI’s award winning Crosscore®  Embedded Studio development tool suite, providing design engineers with interactive, real-time development tools that help optimize their design and speed time to market.Additionally, ADI and Micrium have collaborated to offer µC/OS-II® & µC/OS-III® real-time kernels on both SHARC+ and ARM Cortex-A5 cores, as well as Micrium’s USB Host, USB Device and file system stacks running on the ARM Cortex-A5.Analog Devices also provides the Linux Add-In for CrossCore Embedded Studio, a custom Linux board support package based on Buildroot, enabling customers interested in taking advantage of the communication stacks and application packages available for embedded Linux, running on the ARM Cortex-A5 core.  Target Linux availability is September 2015 and to request, please complete the software request form and specify “Linux SC58x Support' in the Additional Comments field.The ADSP-SC589 EZ-KIT-Lite development board and ICE-1000/2000 emulators facilitate the creation, test, and debug of advanced applications. Working in tandem with CrossCore Embedded Studio, the emulators provide state-of-the-art support for all JTAG-compliant Analog Devices processors now utilizing CoreSight™ from ARM.

Metering Systems on a Chip - SoC Highly Integrated Power and Energy IC

Metering Systems on a Chip - SoC 8 Out Sgl Phase Pwr & Energy Msrmt IC

ANALOG DEVELOPMENT KIT ACCESSORIES;

DEBUGGERS, EMULATORS & JTAG TOOLS;

High-Performance 32-bit Floating-Point SHARC Processor for General Purpose Applications Features: 400MHz SIMD SHARC Core, capable of 2.4 GFLOPS peak performance 2Mbits SRAM; 6 Mbits customer-definable ROM High bandwidth, 32-bit external memory interface supporting glue-less interface to SDRAM, SRAM, and FLASH Digital Audio Interface (DAI) enabling user-definable access to system peripherals including 8 serial ports (SPORTs), S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and 4 precision clock generators. Digital Peripheral Interface (DPI) enabling user-definable access to system peripherals including 2 SPI-compatible ports, 2 UARTs, 3 full-featured timers, and a two-wire interface compliant to the I2C standard. 34 zero-overhead DMA channels 16 Pulse Width Modulation (PWM) channels 208-lead LQFP-EP and 256-ball SBGA packages Commercial and industrial temperature ranges Maximum core performance is reduced for LQFP package

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 800MHz SHARC+ DSP with 640KB L1, 512KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 600MHz (max) or 800MHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 512KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Dual-core SHARC+ DSP (w/768KB L1), 1MB Shared L2, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature range Memory Large on-chip L2 SRAM with ECC protection, up to 1 MBAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications