240MHz ARM Cortex-M4 with 13+ ENOB ADC, BGA212 Features: Dual 16 bit SAR ADCs with no missing codes, 13+ ENOB, 380ns conversion speed for high precision closed loop control. 240 MHz ARM Cortex M4 Core with Floating Point Unit to support advanced programming models and complex algorithms. 384KB SRAM and 2MB flash memory for large program size. Advanced PWM and timer functions for improved torque ripple and motor performance. SINC filters for glueless connection to AD74xx isolated converters. Harmonic Analysis Engine for compliant grid connection. Ethernet and USB to support networked interfaces. Two CAN interfaces, three UARTS, two SPIs, two SPORTs, eight 32-bit timers, two two-wire interfaces and four quadrature encoder interfaces. 16 bit asynchronous memory bus for external SRAM or FPGA interfacing. 212-ball, 19x19mm CSP_BGA package Up to 105C ambient operating temperature for support of industrial applications.

Single-core SHARC+ (w/384KB L1), arm Cortex-A5, 1MB Shared L2, 10/100 Ethernet, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed arm® Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature rangeMemory Large on-chip L2 SRAM with ECC protection, up to 1 MB One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devicesAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

Single-core SHARC+ (w/384KB L1), arm Cortex-A5, 1MB Shared L2, 10/100 Ethernet, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed arm® Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature rangeMemory Large on-chip L2 SRAM with ECC protection, up to 1 MB One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devicesAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

Dual-core SHARC+ and Arm Cortex-A5 SOC, DDR, Ethernet, USB, 349-cspBGA Features:SHARC+ Core Infrastructure: 500 MHz (3.0 GFLOPS) per core 5Mbits/640KB L1 memory/core with parity Optional cache/SRAM mode 32-bit, 40-bit & 64-bit floating point supportARM Core Infrastructure: 450 MHz ARM Cortex-A5 (with Neon/FPU) 32kByte/32kByte L1 Instr./Data Cache 256kByte L2 CacheShared System Memory: 256KB L2 SRAM with ECC protectionUp to Two High Speed Memory Controllers: DDR3-900, DDR2-800 & LPDDR (16-bit)Advanced Hardware Accelerators: FFT/iFFT (20 GFLOPS, 5usec per 1K-pt FFT) FIR/IIR and SINC Filters, ASRC Security Crypto Engines with OTPPackaging: 19mm x 19mm BGA (0.8mm pitch) Commercial, Industrial & AutomotivePeripherals: Gigabit Ethernet MAC (RGMII) With IEEE-1588 & AVB support (QoS & clock recovery) USB2.0 HS OTG/Device Controllers (MAC/PHY) 2x CAN2.0 MLB 3/6-pin (Auto devices only) Up to 8x Full SPORT interfaces (w/ TDM & I2S modes) S/PDIF Tx/Rx, 8x ASRC pairs, PCG 2x Dual-SPI and 1x QuadSPI (w/ direct execution) 3x I2C and 3x UARTs (w/ Flow Control) Enhanced Parallel Peripheral Interface For video I/O or parallel converter interface 2x Link Ports (bi-directional, 8-bit, up to 150MB/sec) 3x Enhanced PWM, ADC Control Module (ACM) 8x GP Timer, 1x GP Counter, WDT and RTC Up to 80 GPIO (mux’ed w/ other interfaces) 8-ch 12-bit 1MSPS Housekeeping ADC Thermal Sensor

Dual-core SHARC+ and ARM Cortex-A5 SOC, dual DDR, 2xEthernet, 2xUSB, SDIO, PCIe, 529-cspBGA Features: 500 MHz (3.0 GFLOPS) per core 5Mbits/640KB L1 memory/core with parity Optional cache/SRAM mode 32-bit, 40-bit & 64-bit floating point supportARM Core Infrastructure: 500 MHz ARM Cortex-A5 (with Neon/FPU) 32kByte/32kByte L1 Instr./Data Cache 256kByte L2 CacheShared System Memory 256KB L2 SRAM with ECC protectionUp to Two High Speed Memory Controllers DDR3-900, DDR2-800 & LPDDR (16-bit)Advanced Hardware Accelerators FFT/iFFT (20 GFLOPS, 5usec per 1K-pt FFT) FIR/IIR and SINC Filters, ASRC Security Crypto Engines with OTPPackaging 19mm x 19mm BGA  (0.8mm pitch) Commercial, Industrial & Automotive 2x Ethernet MAC One Gigabit (RGMII) and one 10/100 (RMII) With IEEE-1588 & AVB support (QoS & clock recovery) 2x USB2.0 HS OTG/Device Controllers (MAC/PHY) 2x CAN2.0 SD/SDIO/MMC/eMMC (with SDXC support) PCIe2.0 (1 lane) (SC589 only) Up to 8 Full SPORT interfaces (w/ TDM & I2S modes) S/PDIF Tx/Rx, 8x ASRC pairs, PCG  2x Dual-SPI and 1x QuadSPI (w/ direct  execution) 3x I2C and 3x UARTs (w/ Flow Control) Enhanced Parallel Peripheral Interface For video I/O or parallel converter interface 2x Link Ports (bi-directional, 8-bit, up to 150MB/sec) 3x Enhanced PWM,  ADC Control Module (ACM) 8x GP Timer, 1x GP Counter, WDT and RTC Up to 102 GPIO (mux’ed w/ other interfaces) 8-ch 12-bit 1MSPS Housekeeping ADC Thermal Sensor

RapID Platform Generation 2 (RPG2) Network Interface Features: Configurable industrial protocol support PROFINET RT (Class B) PROFINET IRT (Class C): coming soon EtherNet/IP with DLR EtherCAT All protocols precertified Configurable applications processor interface UART: 115,200 bps to 1,000,000 bps Ethernet at 10 Mbps or 100 Mbps SPI follower: 10 MHz maximum clock I2C, QSPI, and CAN: future option Industrial Ethernet interface-compliant to IEEE 802.3, 10Base or 100Base transmit half and full duplex Single 3.3 V power supply, 840 mW Cycle time down to 1 ms (cycle times vary based on protocol, link type, and application data) 194-ball chip-scale package BGA form factor RoHS 3 compliant –40°C to +85°C industrial temperature range

RapID Platform Generation 2 (RPG2) Network Interface Features: Configurable industrial protocol support PROFINET RT (Class B) PROFINET IRT (Class C): coming soon EtherNet/IP with DLR EtherCAT All protocols precertified Configurable applications processor interface UART: 115,200 bps to 1,000,000 bps Ethernet at 10 Mbps or 100 Mbps SPI follower: 10 MHz maximum clock I2C, QSPI, and CAN: future option Industrial Ethernet interface-compliant to IEEE 802.3, 10Base or 100Base transmit half and full duplex Single 3.3 V power supply, 840 mW Cycle time down to 1 ms (cycle times vary based on protocol, link type, and application data) 194-ball chip-scale package BGA form factor RoHS 3 compliant –40°C to +85°C industrial temperature range

Configurable Impedance Network Analyzer & Potentiostat with Integrated Cortex M3 Core Features: Analog performance 160 kSPS, 16-bit, precision analog-to-digital converter (ADC) 4 dedicated voltage measurement channels 8 current measurement channels Impedance measurement engine High precision voltage reference Supply noise rejection filtering Ultralow leakage configurable switch matrix 12-bit digital-to-analog converter (DAC) Precision instrumentation amplifier control loop 6-channel CapTouch controller Temperature sensor Analog hardware accelerators Autonomous analog front-end (AFE) controller Independent sequencer for AFE functions Direct digital synthesizer (DDS)/arbitrary waveform generator Receive filters Complex impedance measurement (DFT) engine Processing 16 MHz ARM Cortex-M3 processor 384 kB of embedded flash memory 32 kB system SRAM 16 kB Flash configured EEPROM Integrated full-speed USB 2.0 controller and PHY Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Real-time clock (RTC) General-purpose, wake-up, and watchdog timers Communication Input/output I2S and beeper interface LCD display controller (parallel and serial) LCD segment controller SPI, I2C, and UART peripheral interfaces Programmable GPIOs Power Coin cell battery compatible 2.5 V to 3.6 V active measurement range Power management unit (PMU) Power-on reset (POR) and power supply monitor (PSM) Packages and temperature range Operating temperature range: −40°C to +85°C Package: 120-lead, 8 mm × 8 mm CSP_BGA 

Configurable Impedance Network Analyzer & Potentiostat with Integrated Cortex M3 Core Features: Analog performance 160 kSPS, 16-bit, precision analog-to-digital converter (ADC) 4 dedicated voltage measurement channels 8 current measurement channels Impedance measurement engine High precision voltage reference Supply noise rejection filtering Ultralow leakage configurable switch matrix 12-bit digital-to-analog converter (DAC) Precision instrumentation amplifier control loop 6-channel CapTouch controller Temperature sensor Analog hardware accelerators Autonomous analog front-end (AFE) controller Independent sequencer for AFE functions Direct digital synthesizer (DDS)/arbitrary waveform generator Receive filters Complex impedance measurement (DFT) engine Processing 16 MHz ARM Cortex-M3 processor 384 kB of embedded flash memory 32 kB system SRAM 16 kB Flash configured EEPROM Integrated full-speed USB 2.0 controller and PHY Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Real-time clock (RTC) General-purpose, wake-up, and watchdog timers Communication Input/output I2S and beeper interface LCD display controller (parallel and serial) LCD segment controller SPI, I2C, and UART peripheral interfaces Programmable GPIOs Power Coin cell battery compatible 2.5 V to 3.6 V active measurement range Power management unit (PMU) Power-on reset (POR) and power supply monitor (PSM) Packages and temperature range Operating temperature range: −40°C to +85°C Package: 120-lead, 8 mm × 8 mm CSP_BGA 

3.3 V, 200 Mbps, Half-Duplex, High Speed M-LVDS Transceiver with Type 2 Receiver Features: Multipoint LVDS transceivers (low voltage differential signaling driver and receiver pairs) Switching rate: 200 Mbps (100 MHz) Supported bus loads: 30 to 55 Type 2 receiver type: threshold offset of 100 mV for open-circuit and bus-idle fail-safe Conforms to TIA/EIA-899 standard for M-LVDS Glitch free power-up/power-down on M-LVDS bus Controlled transition times on driver output Common-mode range: −1 V to +3.4 V, allowing communication with 2 V of ground noise Driver outputs high-Z when disabled or powered off See data sheet for additional features