3.3 V, 200 Mbps, Half-Duplex, High Speed M-LVDS Transceiver with Type 2 Receiver Features: Multipoint LVDS transceivers (low voltage differential signaling driver and receiver pairs) Switching rate: 200 Mbps (100 MHz) Supported bus loads: 30 to 55 Type 2 receiver type: threshold offset of 100 mV for open-circuit and bus-idle fail-safe Conforms to TIA/EIA-899 standard for M-LVDS Glitch free power-up/power-down on M-LVDS bus Controlled transition times on driver output Common-mode range: −1 V to +3.4 V, allowing communication with 2 V of ground noise Driver outputs high-Z when disabled or powered off See data sheet for additional features

RapID Platform Generation 2 (RPG2) Network Interface Features: Configurable industrial protocol support PROFINET RT (Class B) PROFINET IRT (Class C): coming soon EtherNet/IP with DLR EtherCAT All protocols precertified Configurable applications processor interface UART: 115,200 bps to 1,000,000 bps Ethernet at 10 Mbps or 100 Mbps SPI follower: 10 MHz maximum clock I2C, QSPI, and CAN: future option Industrial Ethernet interface-compliant to IEEE 802.3, 10Base or 100Base transmit half and full duplex Single 3.3 V power supply, 840 mW Cycle time down to 1 ms (cycle times vary based on protocol, link type, and application data) 194-ball chip-scale package BGA form factor RoHS 3 compliant –40°C to +85°C industrial temperature range

RapID Platform Generation 2 (RPG2) Network Interface Features: Configurable industrial protocol support PROFINET RT (Class B) PROFINET IRT (Class C): coming soon EtherNet/IP with DLR EtherCAT All protocols precertified Configurable applications processor interface UART: 115,200 bps to 1,000,000 bps Ethernet at 10 Mbps or 100 Mbps SPI follower: 10 MHz maximum clock I2C, QSPI, and CAN: future option Industrial Ethernet interface-compliant to IEEE 802.3, 10Base or 100Base transmit half and full duplex Single 3.3 V power supply, 840 mW Cycle time down to 1 ms (cycle times vary based on protocol, link type, and application data) 194-ball chip-scale package BGA form factor RoHS 3 compliant –40°C to +85°C industrial temperature range

High-Performance 32-bit Floating-Point SHARC Processor for General Purpose Applications Features: 400MHz SIMD SHARC Core, capable of 2.4 GFLOPS peak performance 2Mbits SRAM; 6 Mbits customer-definable ROM High bandwidth, 32-bit external memory interface supporting glue-less interface to SDRAM, SRAM, and FLASH Digital Audio Interface (DAI) enabling user-definable access to system peripherals including 8 serial ports (SPORTs), S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and 4 precision clock generators. Digital Peripheral Interface (DPI) enabling user-definable access to system peripherals including 2 SPI-compatible ports, 2 UARTs, 3 full-featured timers, and a two-wire interface compliant to the I2C standard. 34 zero-overhead DMA channels 16 Pulse Width Modulation (PWM) channels 208-lead LQFP-EP and 256-ball SBGA packages Commercial and industrial temperature ranges Maximum core performance is reduced for LQFP package

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 800MHz SHARC+ DSP with 640KB L1, 512KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 600MHz (max) or 800MHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 512KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Dual-core SHARC+ DSP (w/768KB L1), 1MB Shared L2, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature range Memory Large on-chip L2 SRAM with ECC protection, up to 1 MBAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

High Performance Convergent Multimedia Blackfin Processor Features: Lockbox™ Secure Technology: Hardware-enabled security for code and content protection. Two independent DMA controllers Multimedia: Multiple Enhanced Parallel Peripheral Interfaces (EPPI), Pixel Compositor hardware accelerator Human Interface: 18/24-bit LCD Controller 32-bit Up/Down counter / Thumbwheel interface, 8x8 Keypad interface Blackfin® Processor Core with up to 533Mhz (1066 MMACS) performance Connectivity: High Speed USB OTG , Host DMA, UARTs, SPORTs, SPI, TWI, and CAN Expansion: SD/SDIO and ATAPI-6 Controllers Synchronous interface for DDR or Mobile DDR connectivity (See data sheet ordering guide for specific product information) Asynchronous memory interface for SRAM, EEPROM, NAND/NOR, Flash connectivity

Low Power 200MHz Blackfin+ Embedded Processor with 128KByte L2 SRAM & DDR2/LPDDR Interface Features: Blackfin+ core with up to 200 MHz performance Dual 16-bit or single 32-bit MAC support per cycle 16-bit complex MAC and many other instruction set enhancements Instruction set compatible with previous Blackfin product On-Chip Memory 136KB L1 SRAM with multi-parity-bit protection (64KB instruction, 64KB data, 8KB scratchpad) 128KByte on-chip L2 SRAM with ECC protection 512KByte On-chip L2 ROM L3 interface providing 16-bit interface to DDR2 or LPDDR SDRAM devices (up to 200 MHz) Key Peripherals include USB2.0 HS OTG 2x CAN2.0B ePPI Video I/O 2x SPORTs (w/I2S) 2xQuad-SPI / 1xDual-SPI (w/ Host mode option) I2C 2xUART SD/SDIO/MMC (8-bit) 4-ch 12-bit 1MSPS ADC Security and one-time-programmable memory Crypto hardware accelerators for fast secure boot/IP protection memDMA encryption/decryption for fast run-time security Low-cost packaging 184-Ball CSP_BGA package (12 mm × 12mm × 0.8mm pitch), RoHS compliant Low system power with < 53 mW at 200 MHz at 25°C TJUNCTION