The HMC726 is an AND/NAND/OR/NOR function designed to support data transmission rates of up to 13 Gbps, and clock frequencies as high as 13 GHz. The HMC726 may be easily configured to provide any of the following logic functions: AND, NAND, OR and NOR. All input signals to the HMC726 are terminated with 50 Ohms to ground on-chip, and maybe either AC or DC coupled.The differential outputs of the HMC726 may be either AC or DC coupled. Outputs can be connected directly to a 50 Ohm to ground terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ohms to a non-ground DC voltage. The HMC726 operates from a single -3.3V DC supply, dissipates only 230 mW, and is available in a ceramic RoHS compliant 3?3 mm SMT package.APPLICATIONS RF ATE Applications Broadband Test & Measurement Serial Data Transmission?up to 13 Gbps Digital Logic Systems up to 13 GHz

The HMC728 is a 2:1 Selector designed to support data transmission rates of up to 13 Gbps, and selector port operation of up to 13 GHz. The selector routes one of the two single-ended inputs to the differential output upon assertion of the proper select port. All single-ended input signals to the HMC728 are terminated with 50 ohms to ground on-chip, and may be either AC or DC coupled.The outputs of the HMC728 may be operated either differentially or single-ended. Outputs can be connected directly to a 50 ohm terminated system, while DC blocking capacitors may be used if the terminating system is 50 ohms to a non-ground DC voltage. The HMC728 operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS 2:1 Multiplexer up to 13 Gbps F ATE Applications Broadband Test & Measurement Serial Data Transmission up to 13 Gbps Redundant Path Switching Built-in Test

The HMC858LC4B is a 2:1 Selector designed to sup-port data transmission rates of up to 14 Gbps, and selector port operation of up to 14 GHz. The selector routes one of the two differential inputs to the differential output upon assertion of the proper select port. The HMC858LC4B also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All differential input signals to the HMC858LC4B are terminated with 50 ohms to ground on-chip, and may be either AC or DC coupled. The outputs of the HMC858LC4B may be operated either differentially or single-ended. Outputs can be connected directly to a 50 ohm terminated system, while DC blocking capacitors may be used if the terminating system is 50 ohms to a non-ground DC voltage. The HMC858LC4B operates from a single -3.3V DC supply and is available in a ceramic RoHS-compliant, 4?4 mm SMT package.APPLICATIONS 2:1 Multiplexer up to 14 Gbps 16G Fiber Channel Serial Data Transmission?up to 14 Gbps Redundant Path Switching Built-in Test Broadband Test & Measurement

The ADuCM4050WL EZ-KIT® and ADuCM4050LF EZ-KIT®, Analog Devices, Inc. are an evaluation system for the ADuCM4050 MCU, for the WLCSP and LFCSP packages respectively. The ADuCM4050 processor is an ultra low-power integrated mixed-signal microcontroller system for processing, control and connectivity. The MCU system is based on the ARM Cortex-M4F processor. The MCU also has a collection of digital peripherals, embedded SRAM and flash memory, and an analog subsystem which provides clocking, reset, and power management capability in addition to an ADC subsystem. The EZ-KIT contains an array of three connectors that support the ADF7xxx Wireless Transceiver series of daughterboard products. Refer to ADF7xxx Wireless Transceiver Daughterboard Interface for more information. The EZ-KIT contains Expansion Interface 3 (EI3) and Arduino interfaces. These interfaces provide connections for daughterboards to expand the functionality of the EZ-KIT. Refer to Expansion Interface 3 and Arduino Interface for more information. The evaluation board is designed to be used with with the IAR, Keil or CrossCore Embedded Studio development environments for advanced application code development and debug, such as: Create, compile, assemble, and link application programs written in C++, C, and assembly Load, run, step, halt, and set breakpoints in application programs Read and write data and program memory Read and write core and peripheral registers

The ADSP-BF608 Blackfin processor is optimized for embedded vision and video analytics applications using a dual-core fixed-point DSP processor with a unique pipelined vision processor (PVP). The PVP is a set of functional blocks next to the Blackfin cores designed to accelerate image processing algorithms and reduce overall bandwidth requirements.Other features include a high performance enhanced infrastructure, large on-chip memory and a feature rich peripheral set with expanded connectivity options. In addition to these the ADSP-BF608 processor contains features for safety-critical applications, including a CRC for memory protection, Parity and ECC protection in the internal memory blocks and a Fault Management Unit.The ADSP-BF608 processor is ideal for many embedded vision applications such as automotive advanced driver assistance systems (ADAS), machine vision and robotics for industrial manufacturing systems, security and surveillance system analytics and bar code scanners.

The fourth generation of SHARC® Processors, which includes the ADSP-21469, offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21469 offers the highest performance – 450 MHz/2700 MFLOPs -- within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21469 particularly well suited to address the increasing requirements of the professional and automotive audio market segments. In addition to its higher core performance, the ADSP-21469 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to faster external memory by providing a glueless interface to 16-bit wide DDR2 SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The high performance 16/32-bit Blackfin embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the dynamic power management (DPM) functionality allow system designers a flexible platform to address a wide range of portable applications, including consumer, communications and industrial/instrumentation.With the combination of peripherals which enable glue-less connectivity to networked devices such as Ethernet or WiFi 802.11 a/b/g modules and power efficient signal processing, the ADSP-BF526 is well suited to IP connected applications such as VoIP Phone or IP Camera.The VoIP challenge to the embedded-system designer is to choose a processing solution that is cost-effective, easy to deploy and scaleable in performance across market spaces. A “sweet spot” embedded-solution approach is to design with a platform that can implement a low channel count basic VoIP solution, yet retain sufficient capacity for value added capabilities and services – such as video, music, imaging and system control. Unlike traditional VoIP embedded solutions that utilize two processor cores to provide VoIP functionality, the ADSP-BF526 provides a convergent solution in a unified core architecture that allows voice and video signal processing concurrent with RISC MCU processing to handle network and user-interface demands. This unique ability to offer full VoIP functionality on a single convergent processor provides for a unified software development environment, faster system debugging and deployment, and lower overall system cost.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF526 provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.

The AD8197 is an HDMI™/DVI switch featuring equalized TMDS® inputs and pre-emphasized TMDS outputs, ideal for systems with long cable runs. Outputs can be set to a high impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-OR technique. Flexible channel bundling modes (for both the TMDS channels and the auxiliary signals) allow the AD8197 to be configured as a 4:1 single HDMI/DVI link switch, a dual 8:1 switch, or a single 16:1 switch.The AD8197 is provided in a 100-lead LQFP, Pb-free, surface-mount package, specified to operate over the −40°C to +85°C temperature range. ul { margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:15px; padding-top:0px; padding-right:0px; padding-bottom:10px; padding-left:0px;} li { padding-top:0px; padding-right:0px; padding-bottom:5px; padding-left:0px; margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:0px;} ol { margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:25px; padding-top:0px; padding-right:0px; padding-bottom:10px; padding-left:0px;} li { padding-top:0px; padding-right:0px; padding-bottom:5px; padding-left:0px; margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:0px;}Product Highlights Supports data rates up to 2.25 Gbps, enabling 1080p deep color (12-bit color) HDMI formats, and greater than UXGA (1600 × 1200) DVI resolutions. Input cable equalizer enables use of long cables at the input (more than 20 meters of 24 AWG cable at 2.25 Gbps). Auxiliary switch routes a DDC bus and two additional signals for a single-chip, HDMI 1.3 receive-compliant solution.Applications Multiple input displays Projectors A/V receivers Set-top boxes Advanced television (HDTV) sets Data Sheet, Rev. 0, 1/07

The ADSP-21160M DSP is a SHARC processor that is optimized for applications such as telephony, medical imaging, radar/sonar electronics, communications, 3D graphics and imaging. The ADSP-21160M features a Single-Instruction-Multiple-Data (SIMD) architecture.Using two computational units (ALU, Barrel Shifter, MAC, Register files), the ADSP-21160M can have a five fold performance increase versus the ADSP-2106x on a range of DSP algorithms. It is code compatible with ADI's popular first generation ADSP-2106x SHARC DSPs. Like other SHARCs, the ADSP-21160M is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160M includes an 80 MHz core for processing both 32-bit fixed-point and (32-bit, 40-bit) floating-point data types, a dual-ported 4 Mbit on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal busses to eliminate I/O bottlenecks.The ADSP-21160M is optimized for multiprocessing topologies; SHARC supports multiprocessing via link ports or an external port. In the diagram below, both cluster and link port multiprocessing is shown. Over the external port up to six 21160Ms may be connected together without any additional support logic. The arbitration for this shared bus is integrated on-chip. Each SHARC in the cluster has access to every SHARC's internal memory. Through the external port connection, optional external memory may be shared as well.The six link ports are another way to gluelessly connect a multiprocessing system. Both, the links and the cluster can be used simultaneously and systems with hundreds of SHARC DSPs can be developed using both peripherals.Maximize Speed, Minimize Size The ADSP-21160M is offered in a 27mm x 27mm 400-ball PBGA (Plastic Ball Grid Array) package 40% smaller than processors in this performance class.More Processing Per WattIn addition to small size and high performance, the 21160M's power dissipation enables new levels of MFLOPS per watt. The ADSP-21160M typical power dissipation is 2 watts, enabling 240 MFLOPS of performance per watt. This allows designers to use multiple processors on a PCI card within the PCI power limit of 25 watts. With eight 21160M DSPs, providing 480 MFLOPS each, a standard PCI card design can obtain 3.84 GFLOPS performance and leave 9 watts for other circuitry.The ADSP-21160M is supported by hundreds of readily available third-party hardware and software products and ADI's powerful VisualDSP++ development system, allowing for fast and easy development, debug and deployment.

EVALUATION BOARD, SHARC AUDIO PROCESSOR;