White LED Driver with Integrated Schottky in 3mm x 2mm DFN Features: Drives Up to Ten White LEDs from a 3V Supply High Side Sense Allows “One Wire Current Source” Internal Schottky Diode One Pin Dimming and Shutdown 80:1 True Color PWM™ Dimming Range 42V Open LED Protection 1MHz Switching Frequency ±5% Reference Accuracy VIN Range: 2.5V to 12V Requires Only 2.2µF Output Capacitor Low Profile 8-Lead DFN Package (3mm × 2mm × 0.75mm)

3A, DC/DC Converter with Dual Rail-to-Rail Current Sense Features: Dual 100mV Rail-to-Rail Current Sense Amplifiers Wide Input Voltage Range: 2.5V to 25V 3A, 42V Internal Switch High Efficiency Power Conversion: Up to 93% Drives LEDs in Boost, Buck-Boost or Buck Mode Frequency Set by External Resistor: 200kHz to 3.5MHz Programmable Soft-Start Low VCESAT Switch: 0.3V at 2.5A Capable of Positive and Negative Output Voltages (Boost, Inverting, SEPIC, Flyback) Available in Thermally Enhanced 20-Lead (4mm × 4mm) QFN and 20-Lead TSSOP Packages

The AD9880 offers designers the flexibility of an analog interface and High-Definition Multimedia Interface (HDMI™) receiver integrated on a single chip. Also included is support for High bandwidth Digital Content Protection (HDCP).ANALOG INTERFACEThe AD9880 is a complete 8-bit 150 MSPS monolithic analog interface optimized for capturing Component Video (YPbPr) and RGB graphics signals. Its 150 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports all HDTV formats (up to 1080p) and FPD resolutions up to SXGA (1280 × 1024 at 75 Hz).The analog interface includes a 150 MHz triple ADC with internal 1.25V reference, a Phase Locked Loop (PLL), and programmable gain, offset, and clamp control. The user provides only 1.8V and 3.3V power supply, analog input, and Hsync. Three-state CMOS outputs may be powered from 1.8V to 3.3V. The AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 150 MHz. PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The AD9880 also offers full sync processing for composite sync and Sync-on-Green (SOG) applications.DIGITAL INTERFACEThe AD9880 contains a HDMI v1.1 compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 × 1024 at 75 Hz). The receiver features an intra-pair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9880 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP v1.1 protocol.Fabricated in an advanced CMOS process, the AD9880 is provided in a space-saving 100-lead LQFP surface-mount Pb-free plastic package and is specified over the 0 ºC to 70 ºC temperature range.APPLICATIONS Advanced TV HDTV Projectors LCD Monitor

The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully programmable via a 2-wire serial port.Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package. APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV

The AD9887A offers an analog interface receiver and a digital visual interface (DVI) receiver integrated on a single chip, supports high bandwidth digital content protection (HDCP), and is software and pin-to-pin compatible with the AD9887.ANALOG INTERFACEThe complete 8-bit, 170 MSPS, monolithic analog interface is optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 330 MHz support resolutions of up to 1600 × 1200 (UXGA) at 60 Hz. The interface includes a 170 MHz triple ADC with internal 1.25 V reference; a phase-locked loop (PLL); and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and Hsync. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V. The analog interface also offers full sync processing for composite sync and sync-on-green (SOG) applications. The AD9887A on-chip PLL generates a pixel clock from Hsync with output frequencies ranging from 12 MHz to 170 MHz. PLL clock jitter is typically 500 ps p-p at 170 MSPS. DIGITAL INTERFACEThe AD9887A contains a DVI 1.0-compatible receiver and supports resolutions up to 1600 × 1200 (UXGA) at 60 Hz. The receiver operates with true color (24-bit) panels in one or two pixel(s) per clock mode and features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can receive encrypted video content. The AD9887A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of authentication during transmission, as specified by the HDCP v1.0 protocol. Fabricated in an advanced CMOS process, the AD9887A is provided in a 160-lead, surface-mount, plastic MQFP and is specified over the 0°C to 70°C temperature range. The AD9887A is also available in an RoHS compliant package.APPLICATIONS RGB graphics processing LCD monitors and projectors Plasma display panels Scan converters Microdisplays Digital TVs

The ADDI9023 is twelve channel vertical driver for CCD imaging applications. It includes eight 3-level drivers and four 2-level drivers. The input configuration can support up to nine individual vertical timing phases and eight shift gate signals. A separate substrate clock channel (SUBCK) is also included. Typical load drive capability for each channel is 3nF.The ADDI9023 is specified over an operating temperature range of −25°C to +85°C.APPLICATIONS Digital Still Cameras Industrial cameras Surveillance cameras Medical imaging

Laser Drivers 3.3V 622Mbps SDH/SONET

110MHz ANALOG INTFCE FOR SGA FPD

Laser Drivers

Demonstration circuit 2176A features the LT3909, a 2-string × 50mA, 2MHz step-up LED driver with ±1.8% current matching. The LT3909 precisely regulates two LED strings for equal current, supports LED dimming that reduces brightness down to a 1/40,000 ratio, protects against faults and also reports faults. The LT3909 consists of a step-up converter with a fixed 2MHz switching frequency and current sources for the LED strings. The maximum current in each LED string is 40mA. The ISET resistor can be changed to 20.0kΩ to program the string current to 50mA – see the data sheet for an application example with 50mA string current. Voltage feedback resistors optimize operation for LEDs that are 35V maximum.