16-Channel 50mA LED Driver with Buck Controller Features: 6V to 55V Power Input Voltage Range 16 Independent LED Outputs Up to 75mA/36V ±3% LED Current Matching at 50mA (Typ ±1%) 6-Bit Dot Correction Current Adjustment 12-Bit Grayscale PWM Dimming 0.5μs Minimum LED On-Time Adaptive LED Bus Voltage for High Efficiency Cascadable 30MHz Serial Data Interface Full Diagnostic and Protection: Individual Open/Short LED and Overtemperature Fault 40-Lead 6mm × 6mm QFN Package

White LED Driver with Integrated Schottky in 3mm x 2mm DFN Features: Drives Up to Ten White LEDs from a 3V Supply High Side Sense Allows “One Wire Current Source” Internal Schottky Diode One Pin Dimming and Shutdown 80:1 True Color PWM™ Dimming Range 42V Open LED Protection 1MHz Switching Frequency ±5% Reference Accuracy VIN Range: 2.5V to 12V Requires Only 2.2µF Output Capacitor Low Profile 8-Lead DFN Package (3mm × 2mm × 0.75mm)

3A, DC/DC Converter with Dual Rail-to-Rail Current Sense Features: Dual 100mV Rail-to-Rail Current Sense Amplifiers Wide Input Voltage Range: 2.5V to 25V 3A, 42V Internal Switch High Efficiency Power Conversion: Up to 93% Drives LEDs in Boost, Buck-Boost or Buck Mode Frequency Set by External Resistor: 200kHz to 3.5MHz Programmable Soft-Start Low VCESAT Switch: 0.3V at 2.5A Capable of Positive and Negative Output Voltages (Boost, Inverting, SEPIC, Flyback) Available in Thermally Enhanced 20-Lead (4mm × 4mm) QFN and 20-Lead TSSOP Packages

The AD9880 offers designers the flexibility of an analog interface and High-Definition Multimedia Interface (HDMI™) receiver integrated on a single chip. Also included is support for High bandwidth Digital Content Protection (HDCP).ANALOG INTERFACEThe AD9880 is a complete 8-bit 150 MSPS monolithic analog interface optimized for capturing Component Video (YPbPr) and RGB graphics signals. Its 150 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports all HDTV formats (up to 1080p) and FPD resolutions up to SXGA (1280 × 1024 at 75 Hz).The analog interface includes a 150 MHz triple ADC with internal 1.25V reference, a Phase Locked Loop (PLL), and programmable gain, offset, and clamp control. The user provides only 1.8V and 3.3V power supply, analog input, and Hsync. Three-state CMOS outputs may be powered from 1.8V to 3.3V. The AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 150 MHz. PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The AD9880 also offers full sync processing for composite sync and Sync-on-Green (SOG) applications.DIGITAL INTERFACEThe AD9880 contains a HDMI v1.1 compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 × 1024 at 75 Hz). The receiver features an intra-pair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9880 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP v1.1 protocol.Fabricated in an advanced CMOS process, the AD9880 is provided in a space-saving 100-lead LQFP surface-mount Pb-free plastic package and is specified over the 0 ºC to 70 ºC temperature range.APPLICATIONS Advanced TV HDTV Projectors LCD Monitor

The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully programmable via a 2-wire serial port.Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package. APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV

The AD9887A offers an analog interface receiver and a digital visual interface (DVI) receiver integrated on a single chip, supports high bandwidth digital content protection (HDCP), and is software and pin-to-pin compatible with the AD9887.ANALOG INTERFACEThe complete 8-bit, 170 MSPS, monolithic analog interface is optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 330 MHz support resolutions of up to 1600 × 1200 (UXGA) at 60 Hz. The interface includes a 170 MHz triple ADC with internal 1.25 V reference; a phase-locked loop (PLL); and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and Hsync. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V. The analog interface also offers full sync processing for composite sync and sync-on-green (SOG) applications. The AD9887A on-chip PLL generates a pixel clock from Hsync with output frequencies ranging from 12 MHz to 170 MHz. PLL clock jitter is typically 500 ps p-p at 170 MSPS. DIGITAL INTERFACEThe AD9887A contains a DVI 1.0-compatible receiver and supports resolutions up to 1600 × 1200 (UXGA) at 60 Hz. The receiver operates with true color (24-bit) panels in one or two pixel(s) per clock mode and features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can receive encrypted video content. The AD9887A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of authentication during transmission, as specified by the HDCP v1.0 protocol. Fabricated in an advanced CMOS process, the AD9887A is provided in a 160-lead, surface-mount, plastic MQFP and is specified over the 0°C to 70°C temperature range. The AD9887A is also available in an RoHS compliant package.APPLICATIONS RGB graphics processing LCD monitors and projectors Plasma display panels Scan converters Microdisplays Digital TVs

The ADDI9023 is twelve channel vertical driver for CCD imaging applications. It includes eight 3-level drivers and four 2-level drivers. The input configuration can support up to nine individual vertical timing phases and eight shift gate signals. A separate substrate clock channel (SUBCK) is also included. Typical load drive capability for each channel is 3nF.The ADDI9023 is specified over an operating temperature range of −25°C to +85°C.APPLICATIONS Digital Still Cameras Industrial cameras Surveillance cameras Medical imaging

DC1130A: Demo Board for the LT3477 3A, DC/DC Converter with Dual Rail-to-Rail Current Sense.

The ADD5211 is a four-string, white LED driver for backlight applications based on high efficiency, current mode, step-up converter technology. The boost controller drives an external MOSFET switch for step-up regulation from an input voltage of 4.5 V to 40 V and a pin adjustable operating frequency from 200 kHz to 1.2 MHz. An adjustable UVLO function is implemented to reduce input current during power-off.The ADD5211 provides four regulated current sinks for uniform brightness intensity. Each current sink can be driven from 40 mA to 200 mA; the LED driving current is pin adjustable using an external resistor. With an input PWM interface, the ADD5211 drives up to four parallel strings of multiple series connected LEDs.Additional features include LED short protection, LED open protection, boost output short protection, overvoltage protection, cycle-by-cycle current limit, and thermal shutdown for both the IC and the LED array. An open-drain fault output is also included. A programmable soft start is implemented to reduce inrush current during startup. Applications LCD monitor and TV LED backlights Industrial lighting

The HMC7150 is a broadband driver amplifier for electro-absorption modulated lasers (EML) and supports data-rates up to 28.3Gbps to meet the 100Gb Ethernet system requirements. The part provides the module designers scalable power dissipation for varying drive voltage characteristics of different modulators and the power consumption of the module can be set as low as 0.12W to 0.5W at 1.5VP-P and 2.3VP-P outputs amplitudes, respectively. The HMC7150 supports wide range of supply voltages from 3.3V to 6V and delivering excellent time domain performance. The output amplitude and cross-point can be adjusted via control pins. The input and output are 50 Ohms matched and used AC coupled. The HMC7150 is in compact leadless 3x3mm surface mountable package.APPLICATIONS 100Gb Ethernet ER4/ LR4 systems CFP/CFP2/CFP4 or similar form factor modules Optical transceivers and pluggable modules Broadband gain stages and pre-amplifiers Broadband Test & Measurement Equipment