White LED Driver with Integrated Schottky in 3mm x 2mm DFN Features: Drives Up to Ten White LEDs from a 3V Supply High Side Sense Allows “One Wire Current Source” Internal Schottky Diode One Pin Dimming and Shutdown 80:1 True Color PWM™ Dimming Range 42V Open LED Protection 1MHz Switching Frequency ±5% Reference Accuracy VIN Range: 2.5V to 12V Requires Only 2.2µF Output Capacitor Low Profile 8-Lead DFN Package (3mm × 2mm × 0.75mm)

3A, DC/DC Converter with Dual Rail-to-Rail Current Sense Features: Dual 100mV Rail-to-Rail Current Sense Amplifiers Wide Input Voltage Range: 2.5V to 25V 3A, 42V Internal Switch High Efficiency Power Conversion: Up to 93% Drives LEDs in Boost, Buck-Boost or Buck Mode Frequency Set by External Resistor: 200kHz to 3.5MHz Programmable Soft-Start Low VCESAT Switch: 0.3V at 2.5A Capable of Positive and Negative Output Voltages (Boost, Inverting, SEPIC, Flyback) Available in Thermally Enhanced 20-Lead (4mm × 4mm) QFN and 20-Lead TSSOP Packages

16-Channel 50mA LED Driver with Buck Controller Features: 6V to 55V Power Input Voltage Range 16 Independent LED Outputs Up to 75mA/36V ±3% LED Current Matching at 50mA (Typ ±1%) 6-Bit Dot Correction Current Adjustment 12-Bit Grayscale PWM Dimming 0.5μs Minimum LED On-Time Adaptive LED Bus Voltage for High Efficiency Cascadable 30MHz Serial Data Interface Full Diagnostic and Protection: Individual Open/Short LED and Overtemperature Fault 40-Lead 6mm × 6mm QFN Package

36V, 2A Synchronous Step-Up LED Driver Features:±2.5% LED Current Regulation±2% Output Voltage Regulation5000:1 PWM Dimming at 100Hz128:1 Internal PWM DimmingSpread-Spectrum Frequency ModulationSilent Switcher® Architecture for Low EMIOperates in Boost, Buck Mode and Buck-Boost Mode2.8V to 36V Input Voltage RangeUp to 34V LED String Voltage2A, 40V Internal Switches200kHz to 2MHz with SYNC FunctionAnalog or Duty Cycle LED Current ControlOpen/Short LED Protection and Fault IndicationThermally Enhanced 28-Pin (4mm × 5mm) QFN

DISPLAY INTERFACE, 10BIT, 1.9V, LQFP-80; IC Interface Type:I2C; Interface Applications:LCD Monitors and Projectors, Plasma Display Panels, RGB Graphics Processing; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; No. of Pins:80Pins RoHS Compliant: Yes

Charge Pump, 7-Channel Smart LED Driver with I2C Interface Features: Charge pump with automatic gain selection of 1×, 1.5×, and 2× for maximum efficiency 7 independent, programmable LED drivers 7 drivers capable of 30 mA (typical) 1 driver also capable of 60 mA (typical) Programmable maximum current limit (128 levels) Standby mode for <1 μA current consumption 16 programmable fade in and fade out time 0.1 sec to 5.5 sec Choose from linear, square, or cubic rates Fading override I2C-compatible interface for all programming Dedicated reset pin and built-in power-on reset (POR) Short-circuit, overvoltage, and overtemperature protection Internal soft start to limit inrush currents Input-to-output isolation during faults or shutdown Operation down to VIN = 2.5 V with undervoltage lockout (UVLO) at VIN = 2.0 V Available in a small 20-ball, 2.15 mm × 2.36 mm × 0.6 mm WLCSP or a 20-lead, 4 mm × 4 mm × 0.75 mm LFCSP

High Performance 8-Bit Display Interface Features: 8-bit analog-to-digital converters 140 MSPS maximum conversion rate Low PLL clock jitter at 140 MSPS Automatic gain matching Automated offset adjustment 2:1 input mux Power-down via dedicated pin or serial register 4:4:4, 4:2:2, and DDR output format modes Variable output drive strength Odd/even field detection External clock input Regenerated Hsync output

110 MSPS/140 MSPS Analog Interface for Flat Panel Displays Features: Automated clamping level adjustment 140 MSPS maximum conversion rate 300 MHz analog bandwidth 0.5 V to 1.0 V analog input range 500 ps p-p PLL clock jitter at 110 MSPS 3.3 V power supply Full sync processing Sync detect for hot plugging Midscale clamping Power-down mode Low power: 500 mW typical 4:2:2 output format mode

The AD9880 offers designers the flexibility of an analog interface and High-Definition Multimedia Interface (HDMI™) receiver integrated on a single chip. Also included is support for High bandwidth Digital Content Protection (HDCP).ANALOG INTERFACEThe AD9880 is a complete 8-bit 150 MSPS monolithic analog interface optimized for capturing Component Video (YPbPr) and RGB graphics signals. Its 150 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports all HDTV formats (up to 1080p) and FPD resolutions up to SXGA (1280 × 1024 at 75 Hz).The analog interface includes a 150 MHz triple ADC with internal 1.25V reference, a Phase Locked Loop (PLL), and programmable gain, offset, and clamp control. The user provides only 1.8V and 3.3V power supply, analog input, and Hsync. Three-state CMOS outputs may be powered from 1.8V to 3.3V. The AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 150 MHz. PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The AD9880 also offers full sync processing for composite sync and Sync-on-Green (SOG) applications.DIGITAL INTERFACEThe AD9880 contains a HDMI v1.1 compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 × 1024 at 75 Hz). The receiver features an intra-pair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9880 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP v1.1 protocol.Fabricated in an advanced CMOS process, the AD9880 is provided in a space-saving 100-lead LQFP surface-mount Pb-free plastic package and is specified over the 0 ºC to 70 ºC temperature range.APPLICATIONS Advanced TV HDTV Projectors LCD Monitor

The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully programmable via a 2-wire serial port.Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package. APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV