Laser Drivers 3.3V Dual Loop 50Mbps-3.3Gbps

LIGHTING DEVELOPMENT KITS;

The ADN2871 laser diode driver (LDD) is designed for advanced SFP and SFF modules, using SFF-8472 digital diagnostics. The ADN2871 supports operation from 50 Mbps up to 4.25 Gbps.Average power and extinction ratios can be set with a voltage provided by a microcontroller DAC or by a trimmable resistor or digital potentiometer. The average power control loop is implemented using feedback from a monitor photodiode. The device provides bias and modulation current monitoring, as well as fail alarms and automatic laser shutdown (ALS). The device interfaces easily with the Analog Devices, Inc., ADuC7019 and ADuC7020 family of MicroConverter® devices and with the ADN2890, ADN2891, and ADN2892 family of limiting amplifiers to make a complete SFP/SFF transceiver solution. An SFP reference design isavailable.The product is pin-compatible with the ADN2870 dual-loop LDD, allowing the same design to work with either device. For dual-loop control applications, refer to the ADN2870 data sheet. The product is available in a space-saving 4 mm × 4 mm LFCSP specified over the −40°C to +85°C temperature range.Applications 1×/2×/4× Fibre Channel SFP/SFF modules Multirate OC3 to OC48-FEC SFP/SFF modules LX-4 modules DWDM/CWDM SFP modules 1GE SFP/SFF transceiver modules VCSEL, DFB, and FP transmitters

The LT3003 drives three separate strings of LEDs up to 350mA/channel with 3% accurate current matching, resulting in uniform LED brightness and intensity. This approach is superior to conventional methods of running three separate channels with external ballast resistors requiring expensive factory calibration.The LT3003 operates in boost, buck and buck-boost mode. A True Color PWM Dimming ratio of up to 3000:1 is achievable using a logic-level signal at the PWM pin for all modes without the need for external level-shifting circuitry. For applications with input supply above and below the output voltage of the LED strings, the LT3003 allows the LEDs to be returned to the input supply (buck-boost mode) instead of being limited to only SEPIC solutions.The LT3003 is ideal for high power LED driver applications such as TFT LCD backlighting and heads-up displays. Additional overtemperature outputs allow appropriate system management for increased reliability.The LT3003 is available in a small 10-pin MSE package.Applications High Power LED Ballaster Automotive Lighting Video Cameras TFT LCD Backlighting

LED Lighting Development Tools LT3791 4.7V-60V input to drive 25V of LEDs at 2A (scaleable to 100W)

LED Lighting Development Tools LT3475IFE-1 - Dual Step-Down 1.5A LED Dr

LED Lighting Drivers 1.0A LED Flash Driver

LED Lighting Drivers 4 Channel High Current LED Driver with Adaptable Power Control

SPECIALTY / SPECIALIZED INTERFACES;

The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully programmable via a 2-wire serial port.Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package. APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV