Synchronous Buck-Boost High Power White LED Driver Features: High Efficiency: 90% Typical Over Entire Li-Ion Battery Range Wide VIN Range: 2.7V to 5.5V Up to 500mA Continuous Output Current Internal Soft-Start Open/Shorted LED Protection LED Current Matching Typically <2% Constant Frequency 1MHz Operation Low Shutdown Current: 6µA Overtemperature Protection Small Thermally Enhanced 16-Lead (4mm x 4mm) QFN Package

500mA Camera LED Charge Pump Features: Low Noise Constant Frequency Operation High Efficiency: Up to 94% Multi-Mode Operation: 1x, 1.5x or 2x Boost Modes Automatic Mode Switching High Output Current: Up to 500mA Tiny Application Circuit (3mm × 3mm DFN Package All Components <1mm High) Automatic Soft-Start Output Disconnect Open, Shorted LED Protection No Inductors Internal 110m LED Current Sense Resistor 3mm × 3mm 10-Lead DFN Package

IC Multidisplay LED Controller Features: Step-Up/Direct-Connect Fractional Charge Pump Provides Up to 92% Efficiency Up to 400mA Continuous Output Current Independent Current and Dimming Control for 1-6 LED MAIN, 1-4 LED SUB and RGB LED Displays LED Currents Programmable Using 2-Wire I2C™ Serial Interface 1% LED Current Matching Low Noise Constant Frequency Operation* Minimal Component Count Automatic Soft-Start Limits Inrush Current 16 Exponentially Spaced Dimming States Provides 128:1 Brightness Range for MAIN and SUB Displays Up to 4096 Color Combinations for RGB Display Low Operating Current: IVIN = 180µA Tiny, Low Profile 24-Lead (4mm × 4mm × 0.75mm) QFN Package

60V, 1.5A LED Driver with Internal Exponential Scale Dimming Features: Operates in Boost, SEPIC, Buck Mode and Buck-Boost Mode 128:1 Internal Exponential Scale PWM Dimming Wide Input Voltage Range (3V to 60V) 1.5A, 60V Internal Switch 20000:1 External PWM Dimming at 100Hz ±2% LED Current and Output Voltage Regulation PMOS Switch Driver for PWM Dimming LED Short/Open Protection and Indication Constant Voltage and Constant Current Regulation Adjustable 300kHz to 2MHz Switching Frequency Adjustable 100Hz to 1kHz PWM Generator Frequency Internal Spread Spectrum Frequency Modulation Easy Synchronization to External Clock Programmable VIN UVLO with Hysteresis Available in 16-Lead MSOP Package

36V, 2A Synchronous Step-Up LED Driver Features:±2.5% LED Current Regulation±2% Output Voltage Regulation5000:1 PWM Dimming at 100Hz128:1 Internal PWM DimmingSpread-Spectrum Frequency ModulationSilent Switcher® Architecture for Low EMIOperates in Boost, Buck Mode and Buck-Boost Mode2.8V to 36V Input Voltage RangeUp to 34V LED String Voltage2A, 40V Internal Switches200kHz to 2MHz with SYNC FunctionAnalog or Duty Cycle LED Current ControlOpen/Short LED Protection and Fault IndicationThermally Enhanced 28-Pin (4mm × 5mm) QFN

The ADDI9023 is twelve channel vertical driver for CCD imaging applications. It includes eight 3-level drivers and four 2-level drivers. The input configuration can support up to nine individual vertical timing phases and eight shift gate signals. A separate substrate clock channel (SUBCK) is also included. Typical load drive capability for each channel is 3nF.The ADDI9023 is specified over an operating temperature range of −25°C to +85°C.APPLICATIONS Digital Still Cameras Industrial cameras Surveillance cameras Medical imaging

The AD9880 offers designers the flexibility of an analog interface and High-Definition Multimedia Interface (HDMI™) receiver integrated on a single chip. Also included is support for High bandwidth Digital Content Protection (HDCP).ANALOG INTERFACEThe AD9880 is a complete 8-bit 150 MSPS monolithic analog interface optimized for capturing Component Video (YPbPr) and RGB graphics signals. Its 150 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports all HDTV formats (up to 1080p) and FPD resolutions up to SXGA (1280 × 1024 at 75 Hz).The analog interface includes a 150 MHz triple ADC with internal 1.25V reference, a Phase Locked Loop (PLL), and programmable gain, offset, and clamp control. The user provides only 1.8V and 3.3V power supply, analog input, and Hsync. Three-state CMOS outputs may be powered from 1.8V to 3.3V. The AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 150 MHz. PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The AD9880 also offers full sync processing for composite sync and Sync-on-Green (SOG) applications.DIGITAL INTERFACEThe AD9880 contains a HDMI v1.1 compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 × 1024 at 75 Hz). The receiver features an intra-pair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9880 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP v1.1 protocol.Fabricated in an advanced CMOS process, the AD9880 is provided in a space-saving 100-lead LQFP surface-mount Pb-free plastic package and is specified over the 0 ºC to 70 ºC temperature range.APPLICATIONS Advanced TV HDTV Projectors LCD Monitor

The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully programmable via a 2-wire serial port.Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package. APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV

DC871A-A: Demo Board for the LTC3215 700mA Low Noise High Current LED Charge Pump.

Demonstration circuit 2176A features the LT3909, a 2-string × 50mA, 2MHz step-up LED driver with ±1.8% current matching. The LT3909 precisely regulates two LED strings for equal current, supports LED dimming that reduces brightness down to a 1/40,000 ratio, protects against faults and also reports faults. The LT3909 consists of a step-up converter with a fixed 2MHz switching frequency and current sources for the LED strings. The maximum current in each LED string is 40mA. The ISET resistor can be changed to 20.0kΩ to program the string current to 50mA – see the data sheet for an application example with 50mA string current. Voltage feedback resistors optimize operation for LEDs that are 35V maximum.