The ADG901/ADG902 are wideband switches that use a complementary metal-oxide semiconductor (CMOS) process to provide high isolation and low insertion loss to 1 GHz. The ADG901 is an absorptive (matched) switch with 50 ? terminated shunt legs, while the ADG902 is a reflective switch. These devices are designed such that the isolation is high over the dc to 1 GHz frequency range. These switches enable the user to pass dc signals up to 0.5 V without the use of a dc blocking capacitor. They have on-board CMOS control logic, thus eliminating the need for external controlling circuitry. The control inputs are both CMOS and LVTTL compatible. The low power consumption of these CMOS devices makes them ideally suited to wireless applications and general-purpose high frequency switching.Product Highlights 40 dB Off Isolation at 1 GHz 0.8 dB Insertion Loss at 1 GHz 17 dBm P1dB at 1 GHzApplications Wireless communications General purpose RF switching Dual-band applications High speed filter selection Digital transceiver front-end switch IF switching Tuner modules Antenna diversity switching list

The HMC641ALC4 is a broadband non-reflective GaAs pHEMT SP4T switch in a compact 4x4 mm ceramic package. Covering DC to 20 GHz, this switch offers high isolation, low insertion loss and on-chip termination of isolated ports. This switch also includes an on board binary decoder circuit which reduces the number of required logic control lines from four to two. The HMC641ALC4 is controlled with 0/ -5V logic, exhibits fast switching speed and consumes much less DC current than pin diode based solutions.APPLICATIONS Telecom Infrastructure Microwave Radio & VSAT Military & Space Hybrids Test Instrumentation SATCOM & Sensors

Phase Locked Loops - PLL Phase-Locked Oscillator , 14.7-15.4GHz

Attenuators 1 dB LSB 5Bit dig atten Chip 0.1-40 GHz

The ADuCRF101 is a fully integrated, data acquisition solution that is designed for low power, wireless applications. It features a 12-bit analog-to-digital converter (ADC), a low power ARM Cortex?-M3 processor, a 862 MHz to 928 MHz and 431 MHz to 464 MHz RF transceiver, and Flash?/EE memory. The ADuCRF101 is packaged in a 9 mm ? 9 mm LFCSP.The data acquisition section consists of a 12-bit SAR ADC. The six inputs can be configured in single-ended or differential mode. When configured in single-ended mode, they can be used for ratiometric measurements on sensors that are powered, when required, from the internal low dropout regulator (LDO). An internal battery monitor channel and an on-chip temperature sensor are also available.This wireless data acquisition system is designed to operate in battery-powered applications where low power is critical. The device can be configured in normal operating mode or different low power modes under direct program control. In flexi mode, any peripheral can wake up the device and operate it. In hibernate mode, the internal wake-up timer remains active. In shutdown mode, only an external interrupt can wake up the device.The ADuCRF101 integrates a low power ARM Cortex-M3 processor. It is a 32-bit RISC machine, offering up to 1.25 DMIPS peak performance. The ARM Cortex-M3 processor also has a flexible 14-channel direct memory access (DMA) controller that supports communication peripherals, serial peripheral interface (SPI), UART, and I2C. Also provided on chip are 128 kB of nonvolatile Flash/EE memory and 16 kB of SRAM.A 16 MHz on-chip oscillator generates the system clock. This clock can be internally divided for the processor to operate at a lower frequency, thus saving power. A low power, internal 32 kHz oscillator is available and can be used to clock the four timers, as follows: two general-purpose timers, a wake-up timer, and a system watchdog timer.A range of communication peripherals can be configured, as required, in a specific application. These peripherals include UART, I2C, SPI, GPIO ports, PWM, and RF transceivers.The RF transceiver communicates in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands using multiple configurations.On-chip factory firmware supports in-circuit serial download via the UART, and nonintrusive emulation and program download are also supported via the serial wire interface. These features are incorporated into a low cost development system supporting this precision analog microcontroller family.The ADuCRF101 operates from 2.2 V to 3.6 V and is specified over an industrial temperature range of ?40?C to +85?C. It is available in a 64-lead LFCSP packageApplications Battery powered wireless sensor Medical telemetry systems Industrial and home automation Asset tracking Security systems (access systems) Health and fitness applications??

The HMC748 is a 2:1 Selector designed to support data transmission rates of up to 13 Gbps, and selector port operation of up to 13 GHz. The selector routes one of the two single-ended inputs to the differential output upon assertion of the proper select port. The HMC748 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All single-ended input signals to the HMC748 are terminated with 50 ohms to VCC?on-chip, and may be either AC or DC coupled. The outputs of the HMC748 may be operated either differentially or single-ended. Inputs or outputs can be connected directly to a 50 ohm to VCC terminated system, while DC blocking capacitors may be used if the terminating system is 50 ohms to ground. The HMC748 operates from a single +3.3V DC supply and is housed in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS 2:1 Multiplexer up to 13 Gbps RF ATE Applications Broadband Test & Measurement Serial Data Transmission up to 13 Gbps Redundant Path Switching Built-in Test

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

13GHZ FAST RAMP DIRECT MOD FRAC N PLL / REEL7

EVAL BOARD / EB/PCB

EVAL PCB ASSY / EB/PCB