The HMC639ST89(E) is a GaAs PHEMT, High Linearity, Low Noise, Wideband Gain Block Amplifier covering 0.2 to 4.0 GHz. Packaged in an industry standard SOT89, the amplifier can be used as either a cascadable 50 Ohm gain stage, a PA Pre-Driver, a Low Noise Amplifier, or a Gain Block with up to +22 dBm output power. This versatile Gain Block Amplifier is powered from a single +5V supply and requires no external matching components. The internally matched topology permits this amplifier to be readily ported between virtually any printed circuit board material, regardless of its dielectric constant, thickness, or composition.Applications Cellular / PCS / 3G WiMAX, WiBro, & Fixed Wireless CATV & Cable Modem Microwave Radio IF and RF Sections?

HMC750 is a limiting amplifier designed to support data transmission rates up to 12.5 Gbps. The amplifier can operate over a wide range of input voltage levels and provides constant-level differential output swing. HMC750 also features an output level control pin, VC1, which allows for loss compensation or for signal level optimization. Differential output signal swing can be adjustable up to 880 mVp-p. Input signals higher than 3 mVp-p can be amplified to saturated 880 mVp-p differential signal.All single-ended input signals to the HMC750 are terminated with 50 ohms to +5V on-chip, and may be either AC or DC coupled. The outputs of the HMC750 may be operated either differentially or single-ended. Outputs can be connected directly to a 50 ohm terminated system referenced to +5V, while DC blocking capacitors may be used if the terminating system is 50 ??to a non +5V voltage. The HMC750 operates from a single +5V DC supply and is available in a plastic RoHS compliant 4?4 mm SMT package.APPLICATIONS OC-192 Receivers 10 Gbps Ethernet Receivers 10 Gbps Fiber Channel Receivers Broadband Test & Measurement

The HMC748 is a 2:1 Selector designed to support data transmission rates of up to 13 Gbps, and selector port operation of up to 13 GHz. The selector routes one of the two single-ended inputs to the differential output upon assertion of the proper select port. The HMC748 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All single-ended input signals to the HMC748 are terminated with 50 ohms to VCC?on-chip, and may be either AC or DC coupled. The outputs of the HMC748 may be operated either differentially or single-ended. Inputs or outputs can be connected directly to a 50 ohm to VCC terminated system, while DC blocking capacitors may be used if the terminating system is 50 ohms to ground. The HMC748 operates from a single +3.3V DC supply and is housed in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS 2:1 Multiplexer up to 13 Gbps RF ATE Applications Broadband Test & Measurement Serial Data Transmission up to 13 Gbps Redundant Path Switching Built-in Test

The HMC959LC3 is a Divide-by-4 with Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. This results in a divide-by-four function of the clock input. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications. The HMC959LC3 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All input signals to the HMC959LC3 are terminated with 50 ? to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50 ? terminated system, while DC blocking capacitors may be used if the terminating system is 50 ? to a non-ground DC voltage. The HMC959LC3 operates from a single -3.3 V DC supply and is available in a ceramic RoHS-compliant 3?3 mm SMT package.APPLICATIONS High Speed Frequency Divider?(up to 26 GHz) Broadband Test & Measurement Clock Synthesis Phase Locked Loops

The HMC752LC4 is a GaAs MMIC Low Noise WidebandAmplifier housed in a leadless 4x4 mm ceramicsurface mount package. The amplifier operates between24 and 28 GHz, providing up to 25 dB of smallsignal gain, 2.5 dB noise figure, and output IP3 of+26 dBm, while requiring only 70 mA from a +3V supply.The P1dB output power of up to +13 dBm enablesthe LNA to function as a LO driver for balanced, I/Qor image reject mixers. The HMC752LC4 also featuresI/Os that are DC blocked and internally matched to50 Ohms, making it ideal for high capacity microwaveradios or VSAT applications.Applications Point-to-Point Radios Point-to-Multi-Point Radios Military & Space Test Instrumentation

The HMC742A is a digitally controlled variable gain amplifier which operates from 70 MHz to 4 GHz, and can be programmed to provide from -19.5 dB attenuation, to 12 dB of gain, in 0.5 dB steps. The HMC742A delivers noise figure of 4 dB in its maximum gain state, with output IP3 of up to +39 dBm in any state. The dual mode gain control interface accepts either a three-wire serial input or a 6 bit parallel word. The HMC742A also features a user selectable power up state and a serial output for cascading other serially controlled Hittite components. The HMC742A is housed in an RoHS compliant 5x5 mm QFN leadless package, and requires minimal external components.Applications Cellular/3G Infrastructure WiBro / WiMAX / 4G Microwave Radio & VSAT Test Equipment and Sensors IF & RF Applications

The HMC821LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC960LP4E is a digitally programmable dual channel variable gain amplifier. It supports discrete gain steps from 0 to 40 dB in precise 0.5 dB steps. It features a glitch free architecture to provide exceptionally smooth gain transitions. The device has matched gain paths which provide excellent quadrature balance over a wide signal bandwidth.The HMC960LP4E provides an SPI programmable input impedance of 100? differential or 400? differential (default).Externally controlled common mode output feature enables the HMC960LP4E to provide a flexible output interface to other parts in the signal path. Gain can be controlled via either a parallel interface (GC[6:0]) or via the read/write serial port (SPI).Housed in a compact 4x4mm (LP4) SMT QFN package, the HMC960LP4E requires minimal external components and provides a low cost alternative to more complicated switched amplifier architectures.Applications Baseband I/Q Transceivers Direct Conversion &?Low IF Transceivers Diversity Receivers ADC Drivers Adaptive Gain Control

The HMC966LP4E is a compact GaAs MMIC I/Q downconverter in a leadless RoHS compliant SM T package. This device provides a small signal conversion gain of 12 dB with a noise figure of 2.5 dB and 40 dBc of image rejection across the frequency band. The HMC966LP4E utilizes an LNA followed by an image reject mixer which is driven by an active x2 multiplier. The image reject mixer eliminates the need for a filter following the LNA, and removes thermal noise at the image frequency. I and Q mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The HMC966LP4E is a much smaller alternative to hybrid style image reject mixer downconverter assemblies, and is compatible with surface mount manufacturing techniques.Applications Point-to-Point &?Point-to-Multi-Point Radio Military Radar, EW & ELINT Satellite Communications

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers