The HMC960LP4E is a digitally programmable dual channel variable gain amplifier. It supports discrete gain steps from 0 to 40 dB in precise 0.5 dB steps. It features a glitch free architecture to provide exceptionally smooth gain transitions. The device has matched gain paths which provide excellent quadrature balance over a wide signal bandwidth.The HMC960LP4E provides an SPI programmable input impedance of 100? differential or 400? differential (default).Externally controlled common mode output feature enables the HMC960LP4E to provide a flexible output interface to other parts in the signal path. Gain can be controlled via either a parallel interface (GC[6:0]) or via the read/write serial port (SPI).Housed in a compact 4x4mm (LP4) SMT QFN package, the HMC960LP4E requires minimal external components and provides a low cost alternative to more complicated switched amplifier architectures.Applications Baseband I/Q Transceivers Direct Conversion &?Low IF Transceivers Diversity Receivers ADC Drivers Adaptive Gain Control

The HMC966LP4E is a compact GaAs MMIC I/Q downconverter in a leadless RoHS compliant SM T package. This device provides a small signal conversion gain of 12 dB with a noise figure of 2.5 dB and 40 dBc of image rejection across the frequency band. The HMC966LP4E utilizes an LNA followed by an image reject mixer which is driven by an active x2 multiplier. The image reject mixer eliminates the need for a filter following the LNA, and removes thermal noise at the image frequency. I and Q mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The HMC966LP4E is a much smaller alternative to hybrid style image reject mixer downconverter assemblies, and is compatible with surface mount manufacturing techniques.Applications Point-to-Point &?Point-to-Multi-Point Radio Military Radar, EW & ELINT Satellite Communications

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

For a limited time, take a live test drive of the AD6676 by using our?remote evaluation software.The AD6676 is a highly integrated IF subsystem that candigitize radio frequency (RF) bands up to 160 MHz in widthcentered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, theAD6676 relies on a tunable band-pass ?-? ADC with a high oversampling ratio to eliminate the need for band specific IFSAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadraturedigital downconversion followed by selectable decimation filtersreduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interfacesupporting line rates of up to 5.333 Gbps.Applications Wideband cellular infrastructure equipment and repeaters? Point-to-point microwave equipment? Instrumentation? Spectrum and communication analyzers? Software defined radio

The AD6688-3000EBZ supports the AD6688-3000, a 14-bit, 3GSPS dual analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed support direct RF sampling analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD6688 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The device control and subsequent data analyses can now be done using the ACE software package.

The AD8319 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibel-scaled output. It employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in either measurement or controller modes. The AD8319 maintains accurate log conformance for signals of 1 MHz to 8 GHz and provides useful operation to 10 GHz. The input dynamic range is typically 40 dB (re: 50 ?) with error less than ?1 dB. The AD8319 has 8 ns/10 ns response time (fall time/rise time) that enables RF burst detection to a pulse rate of beyond 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V is required to power the device. Current consumption is typically 22 mA, and it decreases to 200 ?A when the device is disabled.?The AD8319 can be configured to provide a control voltage to a power amplifier or a measurement output from the VOUT pin. Because the output can be used for controller applications, special attention was paid to minimize wideband noise. In this mode, the setpoint control voltage is applied to the VSET pin.The feedback loop through an RF amplifier is closed via VOUT, the output of which regulates the amplifier?s output to a magnitude corresponding to VSET. The AD8319 provides 0 V to (VPOS ? 0.1 V) output capability at the VOUT pin, suitable for controller applications. As a measurement device, VOUT is externally connected to VSET to produce an output voltage, VOUT, that is a decreasing linear-in-dB function of the RF input signal amplitude.The logarithmic slope is ?22 mV/dB, determined by the VSET interface. The intercept is 15 dBm (re: 50 ?, CW input) using the INHI input. These parameters are very stable against supply and temperature variations.The AD8319 is fabricated on a SiGe bipolar IC process and is available in a 2 mm ? 3 mm, 8-lead LFCSP_VD for an operating temperature range of ?40?C to +85?C.ApplicationsRF transmitter PA setpoint controls and level monitoring Power monitoring in radiolink transmitters RSSI measurement in base stations, WLANs, WiMAX, and radars

The AD8333 is a dual-phase shifter and I/Q demodulator that enables coherent summing and phase alignment of multiple analog data channels. It is the first solid-state device suitable forbeamformer circuits, such as those used in high performance medical ultrasound equipment featuring CW Doppler. The RF inputs interface directly with the outputs of the dual-channel, low noise preamplifiers included in the?AD8332.A divide-by-4 circuit generates the internal 0? and 90? phases of the local oscillator (LO) that drive the mixers of a pair of matched I/Q demodulators.The AD8333 can be applied as a major element in analog beamformer circuits in medical ultrasound equipment.The AD8333 features an asynchronous reset pin. When used in arrays, the reset pin sets all the LO dividers in the same state. Sixteen discrete phase rotations in 22.5? increments can be selected independently for each channel. For example, if Channel 1 is used as a reference and the RF signal applied to Channel 2 has an I/Q phase lead of 45?, Channel 2 can be phase aligned with Channel 1 by choosing the correct code.Phase shift is defined by the output of one channel relative to another. For example, if the code of Channel 1 is adjusted to 0000 and that of Channel 2 to 0001 and the same signal is applied to both RF inputs, the output of Channel 2 leads that of Channel 1 by 22.5?.The I and Q outputs are provided as currents to facilitate summation. The summed current outputs are converted to voltages by a high dynamic-range, current-to-voltage (I-V) converter, such as the AD8021, configured as a transimpedance amplifier. The resultant signal is then applied to a high resolution ADC, such as the AD7665 (16 bit/570 kSPS).The two I/Q demodulators can be used independently in other nonbeamforming applications. In that case, a transimpedance amplifier is needed for each of the I and Q outputs, four in total for the dual I/Q demodulator.The dynamic range is 159 dB/Hz at each I and Q output, but the following transimpedance amplifier is an important element in maintaining the overall dynamic range, and attention needs to be paid to optimal component selection and design.The AD8333 is available in a 32-lead LFCSP (5 mm ? 5 mm) package for the industrial temperature range of ?40?C to +85?C.Applications Medical imaging (CW ultrasound beamforming) Phased array systems (radar and adaptive antennas) Communication receivers

The AD8349 is high performance quadrature modulator design for use as a single stage up-converter within wireless infrastructure equipment.The AD8349 provides a high output power and very low noise floor supporting a significant improvement in the output signal range. Additionally the excellent phase and amplitude balance accuracy support a higher sideband suppression specification enabling higher order / capacity QAM modulated radios.The AD8349 has been tested for use over the common Cellular bands (900 MHz, 1.9 GHz, 2.1 GHz) meeting the needs as specified by the CDMA/GSM Edge/W-CDMA standards.The AD8349 is supplied in 16-lead Thin Shrunk Small Outline (TSSOP) package, and fully specified over -40?C to 85?C temperature range.APPLICATIONS Cellular/PCS communication systems infrastructure WCDMA/CDMA2000/PCS/GSM/EDGE Wireless LAN/wireless local loop LMDS/broadband wireless access systemsAVAILABILITYSamples (part number AD8349ARE) and an evaluation board (part number AD8349-EVAL) are available. Other Modulator / Demodulator ProductsAD8345 - 250 - 1000 MHz RF / IF Quadrature ModulatorAD8346 - 2.5 GHz Direct Conversion Quadrature ModulatorAD8347 - 800 MHz to 2.7 GHz RF / IF Quadrature DemodulatorAD8348 - 50 - 1000 MHz RF / IF Quadrature Demodulator

The AD8432 is a dual-channel, low power, ultralow noiseamplifier with selectable gain and active impedance matching.Each channel has a single-ended input, differential output, andintegrated input clamps. By pin strapping the gain setting pins, four accurate gains of G = 12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (?4, ?8, ?12, and ?16, respectively) are possible. A bandwidth of200 MHz at G = 12.04 dB makes this amplifier well suited for many high speed applications.The exceptional noise performance of the AD8432 is madepossible by the active impedance matching. Using a feedback network, the input impedance of the amplifiers can be adjusted to match the signal source impedance without compromising the noise performance. Impedance matching and low noise in the AD8432 allow designers to create wider dynamic rangesystems that are able to detect even very low level signals. The AD8432 achieves 0.85 nV/?Hz input-referred voltage noise fora gain of 12.04 dB. The AD8432?s ultralow noise, low distortion, gain accuracy, and channel-to-channel matching are ideal for high performance ultrasound systems and for processing I/Qdemodulator signals.The AD8432 operates on a single supply of 5 V at 24 mA. It isavailable in a 4 mm ? 4 mm, 24-lead LFSCP. The LFCSP featuresan exposed paddle that provides a low thermal resistance path to the PCB, which enables more efficient heat transfer and increasesreliability. The operating temperature range is ?40?C to +85?C.Applications CW Doppler ultrasound front ends? Low noise preamplification? Predriver for I/Q demodulators and phase shifters? Wideband analog-to-digital drivers

The ADL9006 is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), low noise amplifier that operates between 2 GHz and 28 GHz. The amplifier provides 15.5 dB of gain, 2.5 dB noise figure, 26 dBm output third-order intercept (OIP3), and 20 dBm of output power for 1 dB compression (P1dB) while requiring 53 mA from a 5 V supply. The ADL9006 is self biased with only a single positive supply needed to achieve a supply current (IDD) of 53 mA.The ADL9006 amplifier input and output are internally matched to 50 ?.ADL9006CHIPSThe ADL9006CHIPS is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), low noise amplifier that operates from 2 GHz to 28 GHz. The amplifier provides 15.5 dB of gain, 2.2 dB of noise figure, 24 dBm of output third-order intercept (IP3), 20 dBm of output saturated power (PSAT), and 19 dB of power output for 1 dB compression (P1dB) while requiring a 55 mA power supply current (IDD) from a 5 V total supply voltage. The ADL9006CHIPS is self biased with only a single positive supply needed to achieve an IDD of 55 mA.The ADL9006CHIPS amplifier input and output are internally matched to 50 ? facilitating integration into multichip modules (MCMs).APPLICATIONS Test instrumentation Military and space Local oscillator driver amp ADL9006CHIPS Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military and space