The HMC1122 is a 6-bit digital attenuator operating from 0.1 GHz to 6 GHz with a 31.5 dB attenuation control range in 0.5 dB steps.The HMC1122 is implemented in a silicon process, offering very fast settling time, low power consumption, and high ESD robustness. The device features safe state transitions and optimized for excellent step accuracy and high linearity over frequency and temperature range. The RF input and output are internally matched to 50 Ω and do not require any external matching components. The design is bidirectional; therefore, the RF input and output are interchangeable.The HMC1122 operates on a single supply ranging from 3.3 V to 5 V with no performance change due to an on-chip regulator.The device incorporates a driver that provides both serial and parallel control of the attenuator. The device also features a user-selectable power-up state and a serial output port for cascading other serial controlled components.The HMC1122 comes in a RoHS compliant, compact, 4 mm × 4 mm LFCSP package, and is pin compatible to the HMC624A.A fully populated evaluation board is available. Applications Cellular infrastructure Microwave radios and very small aperture terminals (VSATs) Test equipment and sensors IF and RF designs

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

10 GHz to 40 GHz, 1:4 Channel, 4 Frequency Multiplier/Filter Features: 4 input frequency multiplier with programmable harmonic filter Quad Differential Output PAs with independent Enable Control Input Frequency Range: 2.5 GHz to 10 GHz Output Frequency Range: 10 GHz to 40 GHz Input power: 20 dBm (50 ) Output power: 5 dBm differential (100 ) Harmonic rejection: 20 dBc to 40 dBc at all frequencies 3-Wire or 4-Wire SPI Control of all functions On-Chip Programmable State Machines for fast multiplier/filter and transmitter switching and control On-chip temperature sensor, output power detectors, and ADC DC power: 450 mW (2.5 V supply) 6 mm 6 mm, 40-terminal LGA package

400 MHz TO 4000 MHz Low Noise Amplifier Features: Operation from 400 MHz to 4000 MHz Noise figure of 0.8 dB at 900 MHz Requires few external components Integrated active bias control circuit Integrated dc blocking capacitors Adjustable bias for low power applications Single-supply operation from 3 V to 5 V Gain of 20.8 dB at 900 MHz OIP3 of 37.0 dBm at 900 MHz P1dB of 21.8 dBm at 900 MHz Small footprint LFCSP Pin-compatible version with 21.5 dB gain available

21.2 GHz to 23.6 GHz, Low Noise Amplifier Features: Frequency range: 21.2 GHz to 23.6 GHz Typical gain of >22.5 dB Low noise input Noise figure 3.3 dB typical at 21.2 GHz 3.4 dB typical at 23.6 GHz High linearity input ≥1.0 dBm typical input third-order intercept (IIP3) −8 dBm input 1 dB compression point (P1dB) at 23.6 GHz Matched 50 Ω single-ended input Matched 100 Ω differential outputs 8-lead, 2.00 mm × 2.00 mm LFCSP microwave packaging

Integrated Dual RF Transmitter and Observation Receiver Features: Dual transmitters Dual input shared observation Rx Maximum tunable Tx synthesis BW: 450 MHz Maximum observation Rx BW: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multi-chip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range: 75 MHz to 6000 MHz

Integrated, Dual RF Transceiver with Observation Path Features: Dual differential Tx Dual differential Rx Observation receiver with 2 inputs Fully integrated, ultralow power DPD actuator and adaptation engine for PA linearization Sniffer receiver with 3 inputs Tunable range: 300 MHz to 6000 MHz Linearization signal BW to 40 MHz Tx synthesis BW to 250 MHz Rx BW: 8 MHz to 100 MHz Supports FDD and TDD operation Fully integrated independent fractional-N RF synthesizers for Tx, Rx, ORx, and clock generation JESD204B digital interface

46 dBm (40 W), 2.7 GHz to 3.5 GHz, GaN Power Amplifier Features: Frequency range: 2.7 GHz to 3.5 GHz POUT: 46 dBm typical with PIN = 21 dBm at 2.7 GHz to 3.1 GHz Power gain: 25 dB typical with PIN = 21 dBm at 2.7 GHz to 3.1 GHz Small signal gain: 34.5 dB typical at 2.7 GHz to 3.1 GHz PAE: 56% typical with PIN = 21 dBm at 2.7 GHz to 3.1 GHz Supply voltage: VDD = 50 V at IDQ = 300 mA with 10% duty cycle 32-lead, 5 mm × 5 mm LFCSP_CAV package

GaAs, pHEMT, MMIC,1/2 W, 20 GHz to 44 GHz, Power Amplifier Features: Output P1dB: 28 dBm (typical at 34 GHz to 44 GHz) PSAT: 30 dBm (typical at 20 GHz to 34 GHz) Gain: 15 dB (typical at 34 GHz to 44 GHz) IP3: 40 dBm (typical) Supply voltage: 5 V at 600 mA Die size: 2.75 mm × 1.805 mm × 0.1 mm

18 GHz to 44 GHz, GaAs, pHEMT, 32 dBm (>1 W), MMIC Power Amplifier Features:ADPA7005AEHZ Output P1dB: up to 31 dBm typical PSAT: up to 32 dBm typical Gain: up to 15.5 dB typical Output IP3: up to 42.5 dBm typical Supply voltage: 5 V at 1400 mA 50 matched input/output 18-terminal, 7 mm × 7 mm LCC_HS package Integrated power detectorADPA7005CHIP Output P1dB: 31 dBm typical at 20 GHz to 34 GHz PSAT: 32 dBm typical at 20 GHz to 34 GHz Gain: 17 dB typical at 20 GHz to 34 GHz Output IP3: 41 dBm typical at 20 GHz to 34 GHz Supply voltage: 5 V at 1200 mA maximum 50 Ω matched input/output Die size: 3.75 mm × 3.47 mm × 0.1 mm