1 Watt Power Amplifier SMT, 3.3 - 3.8 GHz Features: Gain: 31 dB 40% PAE @ +32.5 dBm pout 2% EVM @ Pout = +22 dBm with 54 Mbps OFDM Signal +46 dBm Output IP3 Integrated Power Control (Vpd) Single +5V Supply

Medium Power Amplifier SMT, 17.5 - 25.5 GHz Features: Gain: 13 dB Saturated Power: +23 dBm @ 26% PAE Supply Voltage: +5V 50 Ohm Matched Input/Output RoHS Compliant 3x3 mm SMT package

Medium Power Amplifier SMT, 5 - 20 GHz Features: Gain: 19 dB Saturated Power: +21 dBm @ 21% PAE Output IP3: +30 dBm Single Supply: +5V @ 114 mA 50 Ohm Matched Input/Output RoHS Compliant 3x3 mm SMT package

1 Watt Power Amplifier SMT, 0.4 - 2.2 GHz Features: Output IP3: +48 dBm 22.5 dB Gain @ 400 MHz 9 dB Gain @ 2100 MHz 53% PAE @ +31 dBm Pout +24 dBm CDMA2000 Channel Power@ -45 dBc ACP Single +5V Supply Integrated Power Control (VPD) QSOP16G SMT Package: 29.4 mm²

HMC474MP86 / HMC474SC70SiGe, HBT gain block amplifiers, SMT, dc to 6 GHz Features: Gain: 15 dB or 15.5 dB P1dB output power: 8 dB Output third-order intercept points (IP3s): 20 dBm or 22 dBm Cascadable 50 inputs/outputs Single supply: 3 V to 10 V Industry standard SC70 Package

InGaP HBT Divide-by-4 SMT, DC - 18 GHz Features: Ultra Low SSB Phase Noise: -150 dBc/Hz Very Wide Bandwidth Output Power: -4 dBm Single DC Supply: +5V 3x3 mm QFN SMT Package

Medium Power Amplifier Chip, 21 - 32 GHz Features: Output IP3: +33 dBm P1dB: +24 dBm Gain: 16 dB Supply Voltage: +5V 50 Ohm Matched Input/Output Die Size: 2.04 x 1.09 x 0.1 mm

Dual Output Low Noise Amplifier, 0.04 - 0.96 GHz Features: Single-ended or Balanced Output High Output IP3: +27 dBm Low Noise Figure: 3.5 dB Single Positive Supply: +5V 75 Ohm Input

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

4T2R Direct RF Transmitter and Observation Receiver Features: Flexible reconfigurable radio common platform design Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R) RFDAC/RFADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RFCLK input option Versatile digital features Configurable digital up/down conversion (DDC and DUC) 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent 48-bit NCO per DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Auxiliary features Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins supporting different user configurations ADC clock driver with selectable divide ratios TDD power savings option and sharing ADCs SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes per each DAC and ADC JESD204B compatible with maximum 15.5 Gbps lane rate JESD204C compatible with maximum 24.75 Gbps lane rate Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch