The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The LTC5530 is an RF power detector for RF applications operating in the 300MHz to 7GHz range. A temperature compensated Schottky diode peak detector and buffer amplifier are combined in a small ThinSOT™ package. The supply voltage range is optimized for operation from a single lithium-ion cell or 3xNiMH.The RF input voltage is peak detected using an on-chip Schottky diode. The detected voltage is buffered and supplied to the VOUT pin. The output buffer gain is set via external resistors. A power saving shutdown mode reduces current to less than 2µA.The LTC5530 operates with input power levels from -32dBm to 10dBm.*Higher frequency operation is achievable with reduced performance. Consult factory for more information.Applications 802.11a, 802.11b, 802.11g, 802.15, 802.16 Multimode Mobile Phone Products Optical Data Links Wireless Data Modems Wireless and Cable Infrastructure RF Power Alarm Envelope Detector

The LT5579 mixer is a high performance upconverting mixer optimized for frequencies in the 1.5GHz to 3.8GHz range. The single-ended LO input and RF output ports simplify board layout and reduce system cost. The mixer needs only –1dBm of LO power and the balanced design results in low LO signal leakage to the RF output. At 2.6GHz operation, the LT5579 provides high conversion gain of 1.3dB, high OIP3 of +26dBm and a low noise floor of –157.5dBm/Hz at a –5dBm RF output signal level. The LT5579 offers a high performance alternative to passive mixers. Unlike passive mixers, which have conversion loss and require high LO drive levels, the LT5579 delivers conversion gain at significantly lower LO input levels and is less sensitive to LO power level variations. The lower LO drive level requirements, combined with the excellent LO leakage performance, translate into lower LO signal contamination of the output signal.Applications GSM/EDGE, W-CDMA, UMTS, LTE and TD-SCDMA Basestations 2.6GHz and 3.5GHz WiMAX Basestations 2.4GHz ISM Band Transmitters High Performance Transmitters

The ADRF6518 is a matched pair of fully differential low noise and low distortion programmable filters and variable gain amplifiers (VGAs). Each channel is capable of rejecting large out-of-band interferers while reliably boosting the wanted signal, thus reducing the bandwidth and resolution requirements on the analog-to-digital converters (ADCs). The excellent matching between channels and their high spurious-free dynamic range over all gain and bandwidth settings make the ADRF6518 ideal for quadrature-based (IQ) communication systems with dense constellations, multiple carriers, and nearby interferers. The various amplifier gains, filter corners and other features are all programmable via a serial port interface (SPI) port.The first VGA that precedes the filters offers 24 dB of continuous gain control with fixed gain options of 9 dB, 12 dB, and 15 dB, and sets a differential input impedance of 400 Ω. The filters provide a six-pole Butterworth response with 0.5 dB corner frequencies from 1 MHz to 63 MHz in 1 MHz steps. For operation beyond 63 MHz, the filter can be disabled and completely bypassed, thereby extending the −3 dB BW up to 1100 MHz. A wideband peak detector is available to monitor the peak signal at the filter inputs. The pair of VGAs that follow the filters each provides 24 dB of continuous gain control with fixed gain options of 12 dB, 15 dB, 18 dB, and 21 dB. The output buffers offer an additional option of 3 dB or 9 dB gain and provide a differential output impedance of less than 10 Ω. They are capable of driving 1.5 V p-p into 400 Ω loads at better than 65 dBc HD3. The output common-mode voltage defaults to VPS/2 and can be adjusted down to 900 mV via the VOCM pin. Independent, built-in dc offset correction loops for each channel can be disabled via the SPI if fully dc-coupled operation is desired. The high-pass corner frequency is determined by external capacitors on the OFS1 and OFS2 pins and the postfilter VGA gain.The ADRF6518 operates from a 3.15 V to 3.45 V supply and consumes a maximum supply current of 400 mA. When fully disabled, it consumes <1 mA. The ADRF6518 is fabricated in an advanced silicon-germanium BiCMOS process and is available in a 32-lead, exposed pad LFCSP. Performance is specified over the −40°C to +85°C temperature range.Applications Point-to-point and point-to-multipoint radios Baseband I/Q receivers Diversity receivers ADC drivers Instrumentation Medical

The AD9361 is a high performance, highly integrated radiofrequency (RF) Agile Transceiver™ designed for use in 3G and4G base station applications. Its programmability and widebandcapability make it ideal for a broad range of transceiver applications.The device combines a RF front end with a flexible mixed-signalbaseband section and integrated frequency synthesizers, simplifyingdesign-in by providing a configurable digital interface to aprocessor. The AD9361 receiver LO operates from 70 MHz to6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHzrange, covering most licensed and unlicensed bands. Channelbandwidths from less than 200 kHz to 56 MHz are supported.The two independent direct conversion receivers have state-of-the-artnoise figure and linearity. Each receive (RX) subsystem includesindependent automatic gain control (AGC), dc offset correction,quadrature correction, and digital filtering, thereby eliminatingthe need for these functions in the digital baseband. The AD9361also has flexible manual gain modes that can be externallycontrolled. Two high dynamic range analog-to-digital converters(ADCs) per channel digitize the received I and Q signals and passthem through configurable decimation filters and 128-tap finiteimpulse response (FIR) filters to produce a 12-bit output signal atthe appropriate sample rate.The transmitters use a direct conversion architecture that achieveshigh modulation accuracy with ultralow noise. This transmitterdesign produces a best in class TX error vector magnitude (EVM)of <−40 dB, allowing significant system margin for the externalpower amplifier (PA) selection. The on-board transmit (TX)power monitor can be used as a power detector, enabling highlyaccurate TX power measurements.The fully integrated phase-locked loops (PLLs) provide lowpower fractional-N frequency synthesis for all receive andtransmit channels. Channel isolation, demanded by frequencydivision duplex (FDD) systems, is integrated into the design.All VCO and loop filter components are integrated.The core of the AD9361 can be powered directly from a 1.3 Vregulator. The IC is controlled via a standard 4-wire serial portand four real-time input/output control pins. Comprehensivepower-down modes are included to minimize power consumptionduring normal use. The AD9361 is packaged in a 10 mm × 10 mm,144-ball chip scale package ball grid array (CSP_BGA).Applications Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems

The AD9364 is a 1 x 1 channel high performance, highly integrated RF Agile Transceiver™. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9364 operates in the 70 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.The AD9364 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA).Applications Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems

The ADF4151 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external voltage controlled oscillator (VCO), loop filter, and external reference frequency.The ADF4151 is used with external VCO parts and is footprint and software compatible with the ADF4350. The part consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider [N = (INT + (FRAC/MOD))]. The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4151 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter.Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V that can be powered down when not in use.The ADF4151 is available in a 5 mm × 5 mm package.Applications Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation

RF Mixer DBL-BAL mix SMT, 0.7 - 2.0 GHz

Sub-GHz Modules lo Noise amp Module, 1.8 - 4.2 GHz

RF Mixer DBL-BAL mix SMT 4.5 - 9.0 GHz