3->5 50Mbps RS-485/RS-422 Transceiver ;RoHS Compliant: Yes

3->5V 50Mbps RS-485/RS-422 Transceiver ;RoHS Compliant: Yes

COM/I&I require low noise LDO w/ 4A rati

FET Input Instrumentation Amplifier

Dual Channel asynchronous evaluation boa ;RoHS Compliant: Yes

Robust 5kV 6 CH digital ISO 3/3

FREQ MULTIPLIER, 14.4-16.4GHZ, QFN-24; F; FREQ MULTIPLIER, 14.4-16.4GHZ, QFN-24; Frequency Min: 14.4GHz; Frequency Max: 16.4GHz; Supply Voltage Min: 4.5V; Supply Voltage Max: 5.5V; RF IC Case Style: QFN; No. of Pins: 24Pins; Operating Temperature Min: -40 C; Packaging: Each

60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller Features: Wide VIN Range: 4.5V to 60V (65V Abs Max) Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 99% • VIN Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE) No External Bootstrap Diodes Required Low Operating IQ: 29μA (One Channel On) Selectable Gate Drive UVLO Thresholds Out-of-Phase Operation Reduces Required Input Capacitance and Power Supply Induced Noise Phase-Lockable Frequency: 75kHz to 850kHz Selectable Continuous, Pulse Skipping or Low Ripple Burst Mode® Operation at Light Loads Selectable Current Limit (LTC3892/LTC3892-2) Very Low Dropout Operation: 99% Duty Cycle Power Good Output Voltage Monitors (LTC3892/LTC3892-2) Low Shutdown IQ: 3.6μA Small 32-Lead 5mm × 5mm QFN Package (LTC3892/LTC3892-2) or TSSOP Package (LTC3892-1)

The ADRF6821 is a highly integrated, dual radio frequency (RF) input, zero intermediate frequency (IF)/low IF RFIC receiverwith a quadrature demodulator, digital step attenuator (DSA),IF linear amplifiers, an integrated, fractional-N phase-locked loop (PLL), and a low phase noise, multicore, voltage controlled oscillator (VCO). The RFIC is ideally suited for communication digital predistortion (DPD) systems.The high isolation 2:1 RF switch and on-chip wideband RFbalun enable the ADRF6821 to support two single-ended, 50 ? terminated RF inputs. A programmable attenuator ensures anoptimal differential RF input level to the high linearity demodulatorcore. The integrated attenuator offers an attenuation range of 15 dB with a step size of 1 dB. High linearity IF amplifiers follow the demodulator and provide an interface to the next componentin the chain, typically an analog-to-digital converter (ADC).The ADRF6821 offers two alternatives for generating thedifferential local oscillator (LO) input signal: internally viathe on-chip fractional-N synthesizer with low phase noiseVCOs or externally via a low phase noise LO signal. Theintegrated synthesizer enables continuous LO coverage from 450 MHz to 2800 MHz. The PLL reference input supports awide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).When selected, the output of the internal fractional-N synthesizeris applied to a divide by 2, quadrature phase splitter. From theexternal LO path, a 2? LO signal can be used with the divide by 2,quadrature phase splitter to generate the quadrature LO inputs to the mixers.The ADRF6821 is fabricated using an advanced silicon germanium(SiGe), bipolar complementary metal oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS compliant,8 mm ? 8 mm LFCSP package with an exposed pad. Performanceis specified over the ?40?C to +105?C case temperature range.Applications Cellular W-CDMA/GSM/LTE DPD receivers? Microwave, point to point radios

IC'S ;ROHS COMPLIANT: YES