16-Bit, 8-Channel,250 kSPS PulSAR ADC Features: Download AD7689-KGD Data Sheet. Available as Known Good Die and fully guaranteed to data sheet specifications. 16-bit resolution with no missing codes 4-channel (AD7682)/8-channel (AD7689) multiplexer with choice of inputs Unipolar single-ended Differential (GND sense) Pseudobipolar Throughput: 250 kSPS INL: ±0.4 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR) Dynamic range: 93.8 dB SINAD: 92.5 dB at 20 kHz THD: −100 dB at 20 kHz Analog input range: 0 V to VREF with VREF up to VDD Multiple reference types Internal selectable 2.5 V or 4.096 V External buffered (up to 4.096 V) External (up to VDD) Internal temperature sensor (TEMP) Channel sequencer, selectable 1-pole filter, busy indicator No pipeline delay, SAR architecture Single-supply 2.3 V to 5.5 V operation with 1.8 V to 5.5 V logic interface Serial interface compatible with SPI, MICROWIRE, QSPI, and DSP Power dissipation 3.5 mW at 2.5 V/200 kSPS 12.5 mW at 5 V/250 kSPS Standby current: 50 nA Low cost grade available 20-lead 4 mm × 4 mm LFCSP package 20-lead 2.4 mm × 2.4 mm WLCSP package

3V/5V, 1 mW, 2-Channel Differential, 16-Bit Sigma-Delta ADC Features: Two Fully Differential Input Channel ADCs Programmable Gain Front End Gains from 1 to 128 Three-Wire Serial Interface SPI®, QSPI™, MICROWIRE™ and DSP Compatible Schmitt Trigger Input on SCLK Ability to Buffer the Analog Input 2.7 V to 3.3 V or 4.75 V to 5.25 V Operation Power Dissipation 1 mW max @ 3 V Standby Current 8 µA max 16-Lead DIP, 16-Lead SOIC and TSSOP Packages

8-Channel, 24-Bit, Simultaneous Sampling ADC Features: 8-channel, 24-bit simultaneous sampling ADC Single-ended or true differential inputs PGA per channel (gains of 1, 2, 4, and 8) Low dc input current ±4 nA (differential)/±8 nA (single-ended) Up to 128 kSPS ODR per channel Programmable ODRs and bandwidth SRC for coherent sampling Sampling rate resolution up to 15.2 × 10−6 SPS Low latency sinc3 and sinc5 filter paths Adjustable phase synchronization Internal 2.5 V reference Two power modes High resolution mode Low power mode Optimizes power dissipation and performance Low resolution SAR ADC for system and chip diagnostics Power supply Bipolar (±1.65 V) or unipolar (3.3 V) supplies Digital I/O supply: 1.8 V to 3.6 V Performance temperature range: −40°C to +105°C Functional temperature range: −40°C to +125°C Performance Combined ac and dc performance 107 dB SNR/dynamic range at 32 kSPS in high resolution mode (sinc5) −109 dB THD ±8 ppm of FSR INL ±15 μV offset error ±0.1% FS gain error ±10 ppm/°C typical temperature coefficient

Dual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface Features: Dual 12-Bit, 2-Channel ADC Fast Throughput Rate 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low Power: 11.4 mW Max at 1 MSPS with 3 V Supplies 24 mW Max at 1 MSPS with 5 V Supplies Wide Input Bandwidth 70 dB SNR at 300 kHz Input Frequency Onboard Reference 2.5 V Flexible Power/Throughput Rate Management Simultaneous Conversion/Read No Pipeline Delays High-Speed Serial Interface SPI®/QSPI™/ MICROWIRE™/DSP Compatible Shut-Down Mode: µA Max 20-Lead TSSOP Package

Low Cost, Low Power, True RMS-to-DC Converter Features: Converts an ac voltage waveform to a dc voltage and then converts to the true rms, average rectified, or absolute value 200 mV rms full-scale input range (larger inputs with input attenuator) High input impedance: 1012 Ω  Low input bias current: 25 pA maximum High accuracy: ±0.3 mV ± 0.3% of reading RMS conversion with signal crest factors up to 5 Wide power supply range: +2.8 V, −3.2 V to ±16.5 V Low power: 200 μA maximum supply current Buffered voltage output No external trims needed for specified accuracy Related device: the AD737 features a power-down control with standby current of only 25 μA; the dc output voltage is negative and the output impedance is 8 kΩ

4MSPS Dual Simultaneous Sampling, 16-BIT SAR ADC, Differential Input Features: 16-bit/14-bit ADC family Dual simultaneous sampling Fully differential analog inputs 4 MSPS throughput conversion rate SNR (typical) 92.5 dB, VREF = 3.3 V external at AD7380 (16-bit) 85.4 dB, VREF = 3.3 V external at AD7381 (14-bit) 101 dB with ×16 OSR On-chip oversampling function Resolution boost function INL (maximum) 2.0 LSBs at 16-bit 1.0 LSB at 14-bit 2.5 V internal reference High speed serial interface −40°C to +125°C operation 16-lead LFCSP, 3 mm × 3 mm Wide common-mode range Alert function

+3/+5 Volt Serial-Input Micropower 12-Bit DAC Features: Micropower - 100 µA Single Supply - 2.7 V to 5.5 V Operation Compact 1.75 mm Height SO-8 Package and 1.1 mm Height TSSOP-8 Package AD7390 - 12-Bit Resolution AD7391 - 10-Bit Resolution SPI and QSPI Serial Interface Compatible with Schmitt Trigger Inputs

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch