The HMC609LC4 is a GaAs PHEMT MMIC Low Noise Amplifier (LNA) which operates from 2 to 4 GHz. The HMC609LC4 features extremely flat performance characteristics including 20 dB of small signal gain, 3.5 dB of noise figure and output IP3 of +36.5 dBm across the operating band. This 50 Ohm matched amplifier does not require any external matching components. The HMC609LC4 is compatible with high volume surface mount manufacturing techniques, and the RF I/Os are DC blocked for further ease of integration.Applications Fixed Microwave Test & Measurement Equipment Radar & Sensors Military & Space

The HMC652LP2E / 653LP2E / 654LP2E / 655LP2E are a line of wideband fixed value SMT 50 Ohm matched attenuators which offer attenuation levels of 2, 3, 4 and 6 dB respectively. These passive attenuators are ideal for military, test equipment, and other wideband applications where extremely flat attenuation, and excellent VSWR vs. frequency are required.These wideband attenuators handle up to +25 dBm of input power, and are compatible with high volume surface mount manufacturing techniques.APPLICATIONS Fiber Optics Microwave Radio Military & Space Test & Measurement Scientific Instruments RF/Microwave Circuit Prototyping

The HMC652LP2E / 653LP2E / 654LP2E / 655LP2E are a line of wideband fixed value SMT 50 Ohm matched attenuators which offer attenuation levels of 2, 3, 4 and 6 dB respectively. These passive attenuators are ideal for military, test equipment, and other wideband applications where extremely flat attenuation, and excellent VSWR vs. frequency are required.These wideband attenuators handle up to +25 dBm of input power, and are compatible with high volume surface mount manufacturing techniques.APPLICATIONS Fiber Optics Microwave Radio Military & Space Test & Measurement Scientific Instruments RF/Microwave Circuit Prototyping

Precision, Rail-to-Rail Input Current Sense Amplifier Features: Very Wide, Over-the-Top®, Input Common Mode Range   - Extends 44V Above V – (Independent of V +)   - Extends –0.3V Below V – Wide Power Supply Range: 2.85V to 36V Input Offset Voltage: 300µV Maximum Gain Accuracy: 1% Max Gain Congurable with External Resistors Operating Current: 150µA Slew Rate: 2V/µs Sense Input Current When Powered Down: 1nA Full-Scale Output Current: 1mA Minimum Operating Temperature Range –40°C to 125°C Available in 2mm × 3mm DFN and 8-Lead MSOP Packages

3V/5V, 1mW, 3-Channel Pseudo Differential, 16-Bit Sigma-Delta ADC Features: Three Pseudo Differential Input Channel ADCs 16 Bits No Missing Codes 0.003% Nonlinearity Programmable Gain Front End Gains from 1 to 128 Three-Wire Serial Interface SPI®, QSPI™, MICROWIRE™ and DSP Compatible Schmitt Trigger Input on SCLK See data sheet for additional features

24-bit, 2 Channel Capacitance to Digital Converter Features:New standard in single chip solutions Interfaces to single or differential floating sensors Resolution down to 4 aF (that is, up to 21 ENOB) Accuracy: 4 fF Linearity: 0.01% Common-mode (not changing) capacitance up to 17 pF Full-scale (changing) capacitance range: 4 pF Tolerant of parasitic capacitance to ground up to 60 pF Update rate: 10 Hz to 90 Hz Simultaneous 50 Hz and 60 Hz rejection at 16 Hz Temperature sensor on-chip Resolution: 0.1C, accuracy: 2C Voltage input channel Internal clock oscillator 2-wire serial interface (I2C-compatible) Power 2.7 V to 5.25 V single-supply operation 0.7 mA current consumption Operating temperature: 40C to +125C 16-lead TSSOP package

3-Channel, Low Noise, Low Power, 16-Bit, Sigma Delta ADC with On-Chip In-Amp Features: RMSnoise:  27 nV at 4.17 Hz (AD7799)  65 nV at 16.7 Hz (AD7799)  40 nV at 4.17 Hz (AD7798)  85 nV at 16.7 Hz (AD7798) Current: 380 μA typical Power-down: 1 μA maximum Low noise, programmable gain, instrumentation amp Internal clock oscillator Simultaneous 50 Hz/60 Hz rejection Reference detect Low-side power switch Programmable digital outputs Burnout currents Power supply: 2.7 V to 5.25 V Update rate: 4.17 Hz to 470 Hz 3 differential inputs

14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP Features: 14-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR) SINAD: 85 dB @ 20 kHz THD: −100 dB @ 20 kHz Pseudo differential analog input range 0 V to VREF with VREF up to VDD No pipeline delay See Data Sheet for Additional Information

16-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common range High common-mode rejection Single-ended to differential conversion 2.048 V input range with 4.096 V REFBUF Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball BGA package 4× footprint reduction versus discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL: 0.4 LSB typical, 1 LSB maximum SINAD: 89 dB typical at 1 kHz THD: 115 dB at 1 kHz, 106 dB at 400 kHz Gain error: 0.005% FS typical Gain error drift: 1 ppm/C maximum On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: 40C to +85C

Three ADCs, One DAC, Low Power Codec with Audio DSPs Features: Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing Tensilica HiFi 3z DSP core Quad MAC per cycle: 24 x 24-bit multiplier and 64-bit accumulator Flexible power operation mode: 24.576 MHz, 49.152 MHz, 73.728 MHz, and 98.304 MHz 336 kB total memory JTAG debug and trace Low latency, 24-bit ADCs and DAC 106 dB SNR (signal through ADC with A-weighted filter) 110 dB combined SNR (signal through DAC and headphone with A-weighted filter) Programmable double precision MAC engine for maximum 24-stage equalizer Serial port sample rates from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 3 differential or single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs Analog differential audio output, configurable as either line output or headphone drive 2 PDM output channels PLL supporting any input clock rate from 30 kHz to 36 MHz 4 channel asynchronous sample rate converters (ASRCs) 2, 16-channel serial audio ports supporting I2S, left justified, right justified, or up to TDM16 (TDM12 in Turbo mode) 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.85 V to 1.21 V Headphone HPVDD at 1.8 V typical Headphone HPVDD_L at 1.2 V to HPVDD Control/communication interfaces I2C, SPI, or UART control ports Master quad SPI (QSPI) UART communication port Self-boot from QSPI flash Flexible GPIO and IRQ 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP